Integrated submicron switching transistor breaking the Si limit at 100V

IET Seminar Digest

Volumn 2008, Issue 2, 2008, Pages

  Desoete, B ^a   Moens, P ^a   Roig, J ^a   Meersman, J ^a   Vanmeerbeek, P ^a   Goessens, C ^a   Baele, J ^a   Backer, E De ^a   Bauwens, F ^a   Tack, M ^a  

^a ON SEMICONDUCTOR   (Belgium)

Author keywords

Integrated power transistor; Si limit; Super junction limit

Indexed keywords

DRIFT REGIONS; GATE OXIDE; HIGH CELL DENSITY; INTEGRATED POWER TRANSISTOR; LOW VOLTAGES; POWER SWITCHING DEVICES; PROCESS PARAMETERS; REVERSE BLOCKING VOLTAGE; SI LIMIT; SILICON LIMIT; SMART POWER TECHNOLOGIES; SPECIFIC-ON-RESISTANCE; SUBMICRON; SUPER-JUNCTION LIMIT; SWITCHING TRANSISTOR; VERTICAL STACKS;

CELL MEMBRANES; ELECTRIC POTENTIAL; GATES (TRANSISTOR); INTERNET SERVICE PROVIDERS; MOS DEVICES; POWER ELECTRONICS; SEMICONDUCTOR JUNCTIONS; SILICON;

TRANSISTORS;

EID: 67650555918     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1049/ic:20080215     Document Type: Conference Paper

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