High performance superjunction UMOSFETs with split p-columns fabricated by multi-ion-implantations

Proceedings of the International Symposium on Power Semiconductor Devices and ICs

Volumn , Issue , 2005, Pages 39-42

  Miura, Yoshinao ^a   Ninomiya, Hitoshi ^a   Kobayashi, Kenya ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC INDUCTORS; ELECTRIC RESISTANCE; ION IMPLANTATION; SEMICONDUCTOR JUNCTIONS; SWITCHING; VOLTAGE CONTROL;

GATE VOLTAGE; SUPERJUNCTIONS; SWITCHING STRESS;

MOSFET DEVICES;

EID: 27744578866     PISSN: 10636854     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. T. Henson, "Low voltage super junction MOSFET simulation and experiment", Proceedings 1SPSD '03, pp. 37-40.
2. M. Kodama. E. Hayashi, Y. Nishibe, and T. Uesugi, "Temperature characteristics of a new 100 V rated power MOSFET, VLMOS", Proceedings ISPSD '04, pp. 463-466.
3. G. E. Koops , E. A. Hijzen, R. J. E. Hueting. and M. A. A. in 't Zandt, "Resurf stepped oxide (RSO) MOSFET for 85 V having a record-low specific on-resislance", Proceedings ISPSD '04 pp. 185-188.
4. H. Ninomiya, Y. Miura, and K. Kobayashi, "Ultra-low on-resistance 60-100 V superjunction UMOSFETs fabricated by multiple ion-implantation", Proceedings ISPSD '04, pp. 177-180.
5. S. Alves, F. Morancho, J-M. Reynes, and B. Lopes, "Vertical N-channel FLIMOSFETs for future 12/42 V dual batteries automotive applications", Proceedings ISPSD '03, pp. 308-311.