Design and implementation of a MicroBlaze-based warp processor

Transactions on Embedded Computing Systems

Volumn 8, Issue 3, 2009, Pages

  Lysecky, Roman ^a   Vahid, Frank ^b  

^a UNIVERSITY OF ARIZONA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Configurable logic; Dynamic optimization; FPGA; Hardware software partitioning; Just in time (JIT) compilation; Soft processor cores; Warp processors

Indexed keywords

CONFIGURABLE LOGIC; DYNAMIC OPTIMIZATION; FPGA; HARDWARE/SOFTWARE PARTITIONING; JUST-IN-TIME (JIT) COMPILATION; SOFT PROCESSOR CORES; WARP PROCESSORS;

COMPUTER AIDED LOGIC DESIGN; JUST IN TIME PRODUCTION; WEAVING;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 67649868080     PISSN: 15399087     EISSN: 15583465     Source Type: Journal    
DOI: 10.1145/1509288.1509294     Document Type: Article

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