A configurable logic architecture for dynamic hardware/software partitioning

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 1, Issue , 2004, Pages 480-485

  Lysecky, Roman ^a   Vahid, Frank ^b  

^a University of California Riverside   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Codesign; Configurable logic; Dynamic optimization; FPGA fabric; Hardware software partitioning; Just in time compilation; Place and route; Platforms; Reconfigurable computing; Self improving chips; Synthesis; System on a chip; Warp processors

Indexed keywords

CODESIGN; CONFIGURABLE LOGIC; DYNAMIC OPTIMIZATION; FPGA FABRIC; HARDWARE/SOFTWARE PARTITIONING; JUST-IN-TIME COMPILATION; PLACE AND ROUTE; PLATFORMS; SELF-IMPROVING CHIPS; SYSTEM-ON-A-CHIP; CO-DESIGNS; RECONFIGURABLE COMPUTING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SOFTWARE; EMBEDDED SYSTEMS; FORMAL LOGIC; MICROPROCESSOR CHIPS; OPTIMIZATION; EXHIBITIONS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); RECONFIGURABLE ARCHITECTURES; SYNTHESIS (CHEMICAL); TOOLS;

FIELD PROGRAMMABLE GATE ARRAYS; HARDWARE;

EID: 3042658598     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268892     Document Type: Conference Paper

References (33)

1. Altera Corp. http://www.altera.com, 2003.
2. Atmel Corp. http://www.atmel.com, 2003.
3. Bala, V., E. Duesterwald, S. Banerjia. Dynamo: A Transparent Dynamic Optimization System. Conf. on Programming Language Design and Implementation, 2000.
4. Balboni, A., W. Fornaciari and D. Sciuto. Partitioning and Exploration in the TOSCA Co-Design Flow. International Workshop on Hardware/Software Codesign, pp. 62-69, 1996.
5. Burger, D., T. Austin. The SimpleScalar Tool Set, version 2.0. SIGARCH Computer Architecture News, Vol. 25, No. 3, 1997.
6. Chow, P., S. Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja. The Design of an SRAM-Based Field-Programmable Gate Array, Part I: Architecture. IEEE Transactions on VLSI Systems, 1999.
7. Cifuentes, C., M. Van Emmerik, D.Ung, D. Simon, T. Waddington. Preliminary Experiences with the Use of the UQBT Binary Translation Framework. Proceedings of the Workshop on Binary Translation, 1999.
8. Critical Blue, http://www.criticalblue.com, 2003.
9. Eles, P., Z. Peng, K. Kuchchinski and A. Doboli. System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search. Kluwer's Design Automation for Embedded Systems, vol2, no 1, pp. 5-32, Jan 1997.
10. Ernst, R., J. Henkel, T. Benner. Hardware-Software Cosynthesis for Microcontrollers. IEEE Design & Test of Computers, pages 64-75, October/December 1993.
11. Gajski, D., F. Vahid, S. Narayan and J. Gong. SpecSyn: An Environment Supporting the Specify-Explore-Refine Paradigm for Hardware/Software System Design. IEEE Trans, on VLSI Systems, Vol. 6, No. 1, pp. 84-100, 1998.
12. Gschwind, M., E. Altman, S. Sathaye, P. Ledak, D. Appenzeller. Dynamic and Transparent Binary Translation. IEEE Computer, Vol. 3, pp.70-77, 2000.
13. Hauck, S., T. Fry, M. Hosler, J. Kao. The Chimaera Reconfigurable Functional Unit. FPGAs for Custom Computing Machines (FCCM), pp. 87-96, 1997.
14. Hauser, J., J. Wawrzynek. Garp: A MIPS processor with a reconfigurable coprocessor. IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), 1997.
15. Henkel, J. A low power hardware/software partitioning approach for core-based embedded systems. Design Automation Conference, pp. 122 - 127,1999.
16. Henkel, J., Y. Li. Energy-conscious HW/SW-partitioning of embedded systems: A Case Study on an MPEG-2 Encoder. Proceedings of Sixth International Workshop on Hardware/Software Codesign, March 1998, pp. 23-27.
17. Henkel, J., R. Ernst. A Hardware/Software Partitioner using a Dynamically Determined Granularity. Design Automation Conference, 1997.
18. Klaiber, A. The Technology Behind Crusoe Processors. Transmeta Corporation White Paper, 2000.
19. Lee, M., H. Singh, G. Lu, N. Bagherzadeh, F. Kurdahi, E. Filho, V. Alves. Design and Implementation of the MorphoSys Reconfigurable Computing Processor. Journal of VLSI Signal Processing-Systems for Signal, Image and Video Technology, 2000.
20. Lysecky, R., F. Vahid. A Codesigned On-chip Logic Minimizer. International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2003.
21. Lysecky, R., F. Vahid. On-chip Logic Minimization. Design Automation Conference (DAC), 2003.
22. Marquardt, A., V. Betz, J. Rose. Speed and Area Trade-offs on Cluster-based FPGA Architectures. IEEE Trans. on VLSI, 2000.
23. Singh, S., J. Rose, P. Chow, D. Lewis. The Effect of Logic Block Architecture on FPGA Performance. IEEE Journal of Solid-State Circuits, Vol. 27, No. 3, 1992.
24. Smit, G., P. Havinga, L. Smit, P. Heysters, M. Rosien. Dynamic Reconfiguration in Mobile Systems. Proc. FPL, 2002.
25. Stitt, G., R. Lysecky, F. Vahid. Dynamic Hardware/Software Partitioning: A First Approach. Design Automation Conference (DAC), 2003.
26. Stitt, G. and F. Vahid. The Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic. IEEE Design and Test of Computers, Nov/Dec 2002.
27. Stitt, G., F. Vahid. Hardware/Software Partitioning of Software Binaries. IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2002.
28. Tensilica, Inc. http://www.tensilica.com, 2003.
29. Triscend Corp. http://www.triscend.com, 2003.
30. Venkataramani, G., W. Najjar, F. Kurdahi, N. Bagherzadeh, W. Bohm. A Compiler Framework for Mapping Applications to a Coarse-grained Reconfigurable Computer Architecture. Conf. on Compiler, Architecture and Synthesis for Embedded Systems (CASES 2001), 2001.
31. Wan, M., Y. Ichikawa, D. Lidsky, L. Rabaey. An Energy Conscious Methodology for Early Design Space Exploration of Heterogeneous DSPs. Proc. ISSS Custom Integrated Circuits Conference (CICC).
32. Wirthlin, M., B. Hutchings. DISC: The Dynamic Instruction Set Compiler. IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), 1995.
33. Xilinx, Inc. http://www.xilinx.com, 2003.