Hardware/software partitioning of software binaries

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 164-170

  Stitt, Greg ^a   Vahid, Frank ^a,b  

^a University of California ^*  (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Assembly language; Binary translation; Codesign; Decompilation; FPGA; Hardware software partitioning; Low power; Synthesis

Indexed keywords

BINARY TRANSLATION; SOFTWARE BINARY LEVEL; SOURCE CODE PARTITIONING;

C (PROGRAMMING LANGUAGE); CODES (SYMBOLS); COMPUTER PROGRAMMING LANGUAGES; ELECTRIC POWER SUPPLIES TO APPARATUS; FIELD PROGRAMMABLE GATE ARRAYS; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; MICROPROCESSOR CHIPS; PROGRAM COMPILERS; SOFTWARE ENGINEERING;

EMBEDDED SYSTEMS;

EID: 0036911691     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774572.774596     Document Type: Conference Paper

References (38)

1. G. Aigner, A. Diwan, D. Heine, M. Lam, D. Moore, B. Murphy, C. Sapuntzakis. An Overview of the SUIF2 Compiler Infrastructure. Computer Systems Laboratory, Standford University.
2. Altera Corporation, ARM-Based Embedded Processor PLDs, August, 2001.
3. P. Athanas, H. Silverman: Processor Reconfiguration Through Instruction-Set Metamorphosis. IEEE Computer, March 1993.
4. Atmel FPSLIC, http://www.atmel.com/atmel/products/prod39.htm.
5. V. Bala, E. Duesterwald, S. Banerjia. Dynamo: A Transparent Dynamic Optimization System. Proc. of the ACM SIGPLAN '00 Conference on Programming Language Design and Implementation, 2000, pp. 1-12.
6. A. Balboni, W. Fornaciari and D. Sciuto. Partitioning and Exploration in the TOSCA Co-Design Flow. International Workshop on Hardware/Software Codesign, pp. 62-69, 1996.
7. W. Böhm, J. Hammes, B. Draper, M. Chawathe, C. Ross, R. Rinker, and W. Najjar. Mapping a Single Assignment Programming Language to Reconfigurable Systems. The Journal of Supercomputing, vol. 21, pp. 117-130, 2002.
8. K. Bondalapati, P. Diniz, P. Duncan, J. Granacki, M. Hall, R. Jain, and H. Ziegler. DEFACTO: A Design Environment for Adaptive Computing Technology. In Reconfigurable Architectures Workshop, RAW'99, April 1999.
9. BRASS Research Group, http://brass.cs.berkeley.edu/.
10. The Cameron Project, http://www.cs.colostate.edu/cameron/.
11. C. Cifuentes, D. Simon, A. Fraboulet. Assembly to High-Level Language Translation. Department of Compter Science and Electrical Engineering, University of Queensland. Technical Report 439, August 1998.
12. C. Cifuentes, M. Van Emmerik, D.Ung, D. Simon, T. Waddington. Preliminary Experiences with the Use of the UQBT Binary Translation Framework. Proceedings of the Workshop on Binary Translation, Newport Beach, USA, October 1999.
13. P. Eles, Z. Peng, K. Kuchchinski and A. Doboli. System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search. Kluwer's Design Automation for Embedded Systems, vol2, no 1, pp. 5-32, Jan 1997.
14. R. Ernst, J. Henkel, T. Benner. Hardware-Software Cosynthesis for Microcontrollers. IEEE Design & Test of Computers, pages 64-75, October/December 1993.
15. D.D. Gajski, F. Vahid, S. Narayan and J. Gong. SpecSyn: An Environment Supporting the Specify-Explore-Refine Paradigm for Hardware/Software System Design. IEEE Transactions on VLSI Systems, Vol. 6, No. 1, pp. 84-100, 1998.
16. R. Goering.Compiler project marks Synopsys' step into post-ASIC world. EE Times, August 28, 2000, http://www.eedesign.com/story/OEG20000828S0020.
17. T. Givargis and F. Vahid, The Platune Platform Tuning Environment, http://www.cs.ucr.edu/~dalton/Platune/, 2002.
18. M. Gokhale, J. Stone. NAPA C: Compiling for hybrid RISC/FPGA architectures. IEEE Symposium on FPGAs for Custom Computing Machines, FCCM '98.
19. J. Hauser, J. Wawrzynek. Garp: a MIPS processor with a reconfigurable coprocessor. IEEE Symposium on FPGAs for Custom Computing Machines, pages 12-21, Napa Valley, CA, April 1997.
20. J. Henkel and R. Ernst. A Hardware/Software Partitioner using a Dynamically Determined Granularity. Design Automation Conference, 1997.
21. J. Henkel, Y. Li. Energy-conscious HW/SW-partitioning of embedded systems: A Case Study on an MPEG-2 Encoder. Proceedings of Sixth International Workshop on Hardware/Software Codesign, March 1998, pp. 23-27.
22. J. Henkel. A low power hardware/software partitioning approach for core-based embedded systems. Proceedings of the 36th ACM/IEEE conference on Design automation conference, pp. 122-127, 1999.
23. Intel StrongArm 1110 Processor, http://developer.intel.com/design/strong.
24. A. Kalavade and E. Lee. A Global Criticality/Local Phase Driven Algorithm for the Constrained Hardware/Software Partitioning Problem. International Workshop on Hardware/Software Codesign, 1994, pp. 42-48.
25. A. Klaiber. The Technology Behind Crusoe Processors. Transmeta Corporation White Paper, January 2000.
26. Y. Li, T. Callahan, E. Darnell, R. Harr, U. Kurkure, and J. Stockwood, Hardware-Software Co-Design of Embedded Reconfigurable Architectures. Proceedings of Design Automation Conf. (DAC), 1999.
27. A. Malik, B. Moyer, D. Cermak. A Low Power Unified Cache Architecture Providing Power and Performance Flexibility. International Symposium on Low Power Electronics and Design. June 2000.
28. MIPS Technologies, Inc., http://www.mips.com.
29. Proceler, http://www.proceler.com
30. R. Gupta, G. De Micheli. Hardware-Software Cosynthesis for Digital Systems. IEEE Design & Test of Computers, pages 29-41, September 1993.
31. C. Snyder. FPGA Processors Ready for Takeoff. Microprocessor Report, November 2000, pp. 25-29.
32. G. Stitt, B. Grattan, J. Villarreall and F. Vahid. Using On-Chip Configurable Logic to Reduce Embedded System Software Energy. IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), 2002.
33. Triscend Corporation, http://www.triscend.com/. 2002.
34. G. Vanmeerbeeck, P. Schaumont, S. Vernalde, M. Engels and I. Bolsens. Hardware/Software Partitioning of Embedded System in OCAPI-x1. International Symposium on Hardware/Software Codesign, pp. 30-35, 2001.
35. J. Villarreal, R. Lysecky, S. Cotterell, K. Miller and F. Vahid. Loop Analysis of Embedded Applications. UC Riverside Technical Report UCR-CSE-01-03, 2001.
36. Virtex Power Estimator, http://support.xilinx.com/cgi-bin/powerweb.pl.
37. M. Wan, Y. Ichikawa, D. Lidsky, J. Rabaey. An energy conscious methodology for early design exploration of heterogeneous DSPs. Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, p. 111-117, Santa Clara, May 1998.
38. Xilinx Corporation, Virtex-II Pro Platform FPGA Handbook, January 31, 2002.