Delay and energy analysis of SEU and EET-tolerant pipeline latches and flip-flops

IEEE Transactions on Nuclear Science

Volumn 56, Issue 3, 2009, Pages 1618-1628

  Blum, Daniel R ^a   Delgado Frias, Josá G ^b  

^a Marvell Semiconductor   (United States)

^b Washington State University   (United States)

Author keywords

Hardened by design; Multiple bit upset; Pipeline flip flops; Radiation effects; Single event transients; Single event upsets

Indexed keywords

90 NM TECHNOLOGY NODE; COMBINATIONAL LOGIC; DIFFERENTIAL STRUCTURE; ENERGY ANALYSIS; ENERGY CONSUMPTION; HARDENED BY DESIGN; LEVEL-SENSITIVE LATCH; MASTER-SLAVE FLIP-FLOP; MULTIPLE-BIT UPSET; SIGNAL ERRORS; SINGLE-ENDED; SINGLE-EVENT TRANSIENTS; SINGLE-EVENT UPSETS;

DESIGN; ELECTRIC NETWORK ANALYSIS; ENERGY MANAGEMENT; FAULT TOLERANCE; FLIP FLOP CIRCUITS; HARDENING; HIGH ELECTRON MOBILITY TRANSISTORS; PIPELINES; QUALITY ASSURANCE; STATIC RANDOM ACCESS STORAGE; TRANSIENTS; URANIUM POWDER METALLURGY;

RADIATION EFFECTS;

EID: 67649221380     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2009.2019590     Document Type: Article

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