Multiple-bit upset analysis in 90 nm SRAMs: Heavy ions testing and 3D simulations

IEEE Transactions on Nuclear Science

Volumn 54, Issue 4, 2007, Pages 904-911

  Giot, Damien ^a   Roche, Philippe ^a   Gasiot, Gilles ^a   Harboe Sørensen, Reno ^b  

^a STMICROELECTRONICS   (France)

^b EUROPEAN SPACE AGENCY   (Netherlands)

Author keywords

Charge sharing; Critical charge; Heavy ions; MOS transistor; Multiple bit upset; Sensitive area; Silicon; Single event upset

Indexed keywords

COMPUTER AIDED DESIGN; HEAVY IONS; MOSFET DEVICES; SILICON; THREE DIMENSIONAL;

CHARGE SHARING; MBU; MULTIPLE-BIT UPSET; SEU; SINGLE-EVENT UPSET;

STATIC RANDOM ACCESS STORAGE;

EID: 34548103489     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2007.902360     Document Type: Conference Paper

References (17)

1. P. Hazucha, T. Karnik, J. Maiz, S. Walstra, B. Bloechel, J. Tschanz, G. Dermer, S. Hareland, P. Armstrong, and S. Borkar, "Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-pm to 90-nm generation," in Tech. Dig. IEEE Int. Electron Devices Meeting (IEDM), Dec. 8-10, 2003, pp. 21.5.1-21.5.4.
2. R. Baumann, "Radiation-induced soft errors in advanced semiconductor technologies," IEEE Trans. Device Mater. Rel., vol. 5, no. 3, pp. 305-316, 2005.
3. E. H. Cannon, D. D. Reinhardt, M. S. Gordon, and P. S. Makowensky, "SRAM SER in 90, 130 and 180 nm bulk and SOI technologies," in Proc. 42nd Annu. IEEE Int. Reliability Physics Symp., Apr. 25-29, 2004, pp. 300-304.
4. Q. X. Zhang, M. D. Hou, J. Liu, Z. G. Wang, Y. F. Jin, Z. Y. Zhu, and Y. M. Sun, "The impact of incident angle on multiple bit upset in SRAMs," in NIMB, 2003 [Online], Available: www.elsevier.com/locate/nimb
5. P. Roche, G. Gasiot, K. Forbes, V. O'Sullivan, and V. Ferlet, "Comparison of soft error rate for SRAMs in commercial SOI and bulk below the 130-nm technology node," IEEE Trans. Nucl. Sci., vol. 50, pp. 2046-2454, Dec. 2003.
6. J. Maiz, S. Hareland, K. Zhang, and P. Armstrong, "Characterization of multi-bit soft error events in advanced SRAMs," in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 8-10, 2003, pp. 21.4.1-21.4.4.
7. Y. Tosaka, H. Ehara, M. Igeta, T. Uemura, H. Oka, N. Matsuoka, and K. Hatanaka, "Comprehensive study of soft errors in advanced CMOS circuits with 90/130 nm technology," in Proc. IEEE Int. Election Devices Meeting (IEDM), Dec. 2004, vol. 13-15, pp. 941-944.
8. P. Roche, F. Jacquet, C. Caillat, and J. P. Schoellkopf, "An alpha immune and ultra low neutron SER high density SRAM," in Pioc. IRPS, Apr. 2004, pp. 671-672.
9. P. Roche and G. Gasiot, "Impacts of front-end and middle-end process modifications on terrestrial soft error rate," IEEE Trans. Device Mater. Rel., vol. 5, pp. 382-396, Sep. 2005.
10. G. Gasiot, D. Giot, and P. Roche, "Alpha-induced multiple cell upsets in standard and radiation hardened SRAMs manufactured in a 65 nm CMOS technology," IEEE Trans. Nucl. Sci., vol. 53, no. 6, pt. 1, pp. 3479-3486, Dec. 2006.
11. J. D. Black, A. L. Sternberg, M. L. Alles, A. F. Witulski, B. L. Bhuva, L. W. Massengill, J. M. Benedetto, M. P. Base, J. L. Wert, and M. G. Hubert, "HBD layout isolation techniques for multiple node charge collection mitigation," IEEE Trans. Nucl. Sci., vol. 52, pp. 2536-2541, Dec. 2005.
12. P. Oldiges, K. Bernstein, D. Heidel, B. Klaasen, E. Cannon, R. Dennard, H. Tang, M. Ieong, and H.-S. P. Wong, "Soft error rate scaling for emerging SOI technology options," in 2002 Symp. VLSI Technology, Dig. of Tech. Papers, Jun. 11-13, 2002, pp. 46-47.
13. R. Baumann, "The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction," in Int. Electron Device Meeting (IEDM), 2002, pp. 329-332.
14. A. Virtanen, R. Harboe-Sorensen, H. Koivisto, S. Pirojenko, and K. Ranttila, "High penetration, heavy ions at the RADEF test site," in Proc. 7th Eur. Conf. Radiation and Its Effects on Components Systems (RADECS), Sep. 15-19, 2003, pp. 499-450.
15. P. Roche, J. M. Palau, G. Bruguier, C. Tavernier, R. Ecoffet, and J. Gasiot, "Determination of key parameters for SEU occurrence using 3-D full cell SRAM simulations," IEEE Trans. Nucl. Sci., vol. 46, no. 6, pp. 1354-1362, Dec. 1999.
16. P. Dodd, M. R. Shaneyfield, K. M. Horn, D. S. Walsh, G. L. Hash, T. A. Hill, B. L. Draper, J. R. Schwank, F. W. Sexton, and P. S. Winokur, "SEU-sensitive volumes in bulk and SOI SRAMs from first principles calculations and experiments," IEEE Trans. Nucl. Sci., vol. 48, pp. 1893-1903, Dec. 2001.
17. J. C. Pickel, "Cosmic ray induced errors in MOS memory cells," IEEE Trans. Nucl. Sci., vol. NS-25, 1978.