-
1
-
-
67349278992
-
-
V. Narayanan, V. K. Paruchuri, N. A. Bojarczuk, B. P. Linder, B. Doris, Y. H. Kim, S. Zafar, J. Stathis, S. Brown, J. Arnold, M. Copel, M. Steen, E. Cartier, A. Callegari, P. Jamison, J.-P. Locquet, D. L. Lacey, Y. Wang, P. E. Batson, P. Ronsheim, R. Jammy, M. P. Chudzik, M. Ieong, S. Guha, G. Shahidi, and T. C. Chen, Band-edge high-performance high-κ/metal gate n-MOSFETs using cap layers containing group IIA and IIIB elements with gate-first processing for 45 nm and beyond, in VLSI Symp. Tech. Dig., Jun. 2006, pp. 224-225.
-
V. Narayanan, V. K. Paruchuri, N. A. Bojarczuk, B. P. Linder, B. Doris, Y. H. Kim, S. Zafar, J. Stathis, S. Brown, J. Arnold, M. Copel, M. Steen, E. Cartier, A. Callegari, P. Jamison, J.-P. Locquet, D. L. Lacey, Y. Wang, P. E. Batson, P. Ronsheim, R. Jammy, M. P. Chudzik, M. Ieong, S. Guha, G. Shahidi, and T. C. Chen, "Band-edge high-performance high-κ/metal gate n-MOSFETs using cap layers containing group IIA and IIIB elements with gate-first processing for 45 nm and beyond," in VLSI Symp. Tech. Dig., Jun. 2006, pp. 224-225.
-
-
-
-
2
-
-
33645217470
-
-
x(N) achieved by adjusting Hf/Al compositional ratio, J. Appl. Phys., 99, no. 5, pp. 054 506-1-054 506-6, Mar. 2006.
-
x(N) achieved by adjusting Hf/Al compositional ratio," J. Appl. Phys., vol. 99, no. 5, pp. 054 506-1-054 506-6, Mar. 2006.
-
-
-
-
3
-
-
40949130851
-
Dipole moment model explaining nFET Vt tuning utilizing La, Sc, Er, and Sr doped HfSiON dielectrics
-
Jun
-
P. Sivasubramani, T. S. Böscke, J. Huang, C. D. Young, P. D. Kirsch, S. A. Krishnan, M. A. Quevedo-Lopez, S. Govindarajan, B. S. Ju, H. R. Harris, D. J. Lichtenwalner, J. S. Jur, A. I. Kingon, J. Kim, B. E. Gnade, R. M. Wallace, G. Bersuker, B. H. Lee, and R. Jammy, "Dipole moment model explaining nFET Vt tuning utilizing La, Sc, Er, and Sr doped HfSiON dielectrics," in VLSI Symp. Tech. Dig., Jun. 2007, pp. 68-69.
-
(2007)
VLSI Symp. Tech. Dig
, pp. 68-69
-
-
Sivasubramani, P.1
Böscke, T.S.2
Huang, J.3
Young, C.D.4
Kirsch, P.D.5
Krishnan, S.A.6
Quevedo-Lopez, M.A.7
Govindarajan, S.8
Ju, B.S.9
Harris, H.R.10
Lichtenwalner, D.J.11
Jur, J.S.12
Kingon, A.I.13
Kim, J.14
Gnade, B.E.15
Wallace, R.M.16
Bersuker, G.17
Lee, B.H.18
Jammy, R.19
-
4
-
-
67349175468
-
FB shift in high-k CMOS - Dipole formation, Fermi-level pinning and oxygen vacancy effect
-
Dec
-
FB shift in high-k CMOS - Dipole formation, Fermi-level pinning and oxygen vacancy effect," in IEDM Tech. Dig., Dec. 2007, pp. 307-310.
-
(2007)
IEDM Tech. Dig
, pp. 307-310
-
-
Kamimuta, Y.1
Iwamoto, K.2
Nunoshige, Y.3
Hirano, A.4
Mizubayashi, W.5
Watanabe, Y.6
Migita, S.7
Ogawa, A.8
Ota, H.9
Nabatame, T.10
Toriumi, A.11
-
5
-
-
33644772724
-
2 gate dielectric
-
Jun
-
2 gate dielectric," in VLSI Symp. Tech. Dig., Jun. 2005, pp. 50-51.
-
(2005)
VLSI Symp. Tech. Dig
, pp. 50-51
-
-
Zhang, Z.B.1
Song, S.C.2
Huffman, C.3
Barnett, J.4
Moumen, N.5
Alshareef, H.6
Majhi, P.7
Hussain, M.8
Akbar, M.S.9
Sim, J.H.10
Bae, S.H.11
Sassman, B.12
Lee, B.H.13
-
6
-
-
67349222685
-
Full-metal-gate integration of dual-metal-gate HfSiON CMOS transistors by using oxidation-free dummy-mask process
-
Sep
-
F. Ootsuka, Y. Tamura, Y. Akasaka, S. Inumiya, H. Nakata, M. Ohtsuka, T. Watanabe, M. Kitajima, Y. Nara, and K. Nakamura, "Full-metal-gate integration of dual-metal-gate HfSiON CMOS transistors by using oxidation-free dummy-mask process," in Proc. SSDM, Sep. 2006, pp. 862-863.
-
(2006)
Proc. SSDM
, pp. 862-863
-
-
Ootsuka, F.1
Tamura, Y.2
Akasaka, Y.3
Inumiya, S.4
Nakata, H.5
Ohtsuka, M.6
Watanabe, T.7
Kitajima, M.8
Nara, Y.9
Nakamura, K.10
-
7
-
-
50249097266
-
Single metal/dual high-k gate stack with low Vth and precise gate profile control for highly manufacturable aggressively scaled CMISFETs
-
Dec
-
N. Mise, T. Morooka, T. Eimori, S. Kamiyama, K. Murayama, M. Sato, T. Ono, Y. Nara, and Y. Ohji, "Single metal/dual high-k gate stack with low Vth and precise gate profile control for highly manufacturable aggressively scaled CMISFETs," in IEDM Tech. Dig., Dec. 2007, pp. 527-530.
-
(2007)
IEDM Tech. Dig
, pp. 527-530
-
-
Mise, N.1
Morooka, T.2
Eimori, T.3
Kamiyama, S.4
Murayama, K.5
Sato, M.6
Ono, T.7
Nara, Y.8
Ohji, Y.9
-
8
-
-
33644620726
-
TiN metal gate thickness influence on fully depleted SOI MOSFETs physical and electrical properties
-
J. Widiez, M. Vinet, T. Poiroux, P. Holliger, B. Previtali, P. Grosgeorges, M. Mouis, and S. Deleonibus, "TiN metal gate thickness influence on fully depleted SOI MOSFETs physical and electrical properties," in Proc. IEEE Int. SOI Conf., 2005, pp. 30-31.
-
(2005)
Proc. IEEE Int. SOI Conf
, pp. 30-31
-
-
Widiez, J.1
Vinet, M.2
Poiroux, T.3
Holliger, P.4
Previtali, B.5
Grosgeorges, P.6
Mouis, M.7
Deleonibus, S.8
-
9
-
-
46049085229
-
Highly manufacturable singlemetal gate process using ultra-thin metal inserted poly-Si stack (UT-MIPS)
-
Dec
-
S. K. Han, H. S. Jung, H. Lim, M. J. Kim, C. K. Lee, M. S. Lee, Y. S. You, H. S. Baik, Y. S. Chung, E. Lee, J. H. Lee, N. I. Lee, and H. K. Kang, "Highly manufacturable singlemetal gate process using ultra-thin metal inserted poly-Si stack (UT-MIPS)," in IEDM Tech. Dig., Dec. 2006, pp. 621-624.
-
(2006)
IEDM Tech. Dig
, pp. 621-624
-
-
Han, S.K.1
Jung, H.S.2
Lim, H.3
Kim, M.J.4
Lee, C.K.5
Lee, M.S.6
You, Y.S.7
Baik, H.S.8
Chung, Y.S.9
Lee, E.10
Lee, J.H.11
Lee, N.I.12
Kang, H.K.13
-
10
-
-
47249139076
-
Advanced poly-Si NMIS and poly-Si/TiN PMIS hybrid-gate high-k CMIS using PVD/CVD-stacked TiN and local strain technique
-
Jun
-
Y. Nishida, T. Kawahara, S. Sakashita, M. Mizutani, S. Yamanari, M. Higashi, N. Murata, M. Inoue, J. Yugami, S. Endo, T. Hayashi, T. Yamashita, H. Oda, and Y. Inoue, "Advanced poly-Si NMIS and poly-Si/TiN PMIS hybrid-gate high-k CMIS using PVD/CVD-stacked TiN and local strain technique," in VLSI Symp. Tech. Dig., Jun. 2007, pp. 214-215.
-
(2007)
VLSI Symp. Tech. Dig
, pp. 214-215
-
-
Nishida, Y.1
Kawahara, T.2
Sakashita, S.3
Mizutani, M.4
Yamanari, S.5
Higashi, M.6
Murata, N.7
Inoue, M.8
Yugami, J.9
Endo, S.10
Hayashi, T.11
Yamashita, T.12
Oda, H.13
Inoue, Y.14
-
11
-
-
0003998388
-
-
75th ed. D. R. Lide, Ed. Boca Raton, FL: CRC Press
-
CRC Handbook of Chemistry and Physics, 75th ed. D. R. Lide, Ed. Boca Raton, FL: CRC Press, 1994-1995, pp. 12-113-12-114.
-
(1994)
CRC Handbook of Chemistry and Physics
-
-
-
12
-
-
0030086048
-
Formation and stability of silicides on polycrystalline silicon
-
Feb
-
E. G. Colgan, J. P. Gambino, and Q. Z. Hong, "Formation and stability of silicides on polycrystalline silicon," Mat. Sci. Eng. R: Rep., vol. 16, no. 2, pp. 43-96, Feb. 1996.
-
(1996)
Mat. Sci. Eng. R: Rep
, vol.16
, Issue.2
, pp. 43-96
-
-
Colgan, E.G.1
Gambino, J.P.2
Hong, Q.Z.3
-
13
-
-
0001121777
-
Schottky barrier height - Do we really understand what we measure?
-
Jul
-
R. T. Tung, "Schottky barrier height - Do we really understand what we measure?" J. Vac. Sci. Technol. B, Microelectron. Process. Phenom. vol. 11, no. 4, pp. 1546-1552, Jul. 1993.
-
(1993)
J. Vac. Sci. Technol. B, Microelectron. Process. Phenom
, vol.11
, Issue.4
, pp. 1546-1552
-
-
Tung, R.T.1
-
14
-
-
52349118774
-
-
S. Kubicek, T. Schram, E. Rohr, V. Paraschiv, R. Vos, M. Demand, C. Adelmann, T. Witters, L. Nyns, A. Delabie, L. Å. Ragnarsson, T. Chiarella, C. Kerner, A. Mercha, B. Parvais, M. Aoulaiche, C. Ortolland, H. Yu, A. Veloso, L. Witters, R. Singanamalla, T. Kauerauf, S. Brus, C. Vrancken, V. S. Chang, S. Z. Chang, R. Mitsuhashi, Y. Okuno, A. Akheyar, H. J. Cho, J. Hooker, B. J. O'Sullivan, S. Van Elshocht, K. De Meyer, M. Jurczak, P. Absil, S. Biesemans, and T. Hoffmann, Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10 ps invertor delay, in VLSI Symp. Tech. Dig., Jun. 2008, pp. 130-131.
-
S. Kubicek, T. Schram, E. Rohr, V. Paraschiv, R. Vos, M. Demand, C. Adelmann, T. Witters, L. Nyns, A. Delabie, L. Å. Ragnarsson, T. Chiarella, C. Kerner, A. Mercha, B. Parvais, M. Aoulaiche, C. Ortolland, H. Yu, A. Veloso, L. Witters, R. Singanamalla, T. Kauerauf, S. Brus, C. Vrancken, V. S. Chang, S. Z. Chang, R. Mitsuhashi, Y. Okuno, A. Akheyar, H. J. Cho, J. Hooker, B. J. O'Sullivan, S. Van Elshocht, K. De Meyer, M. Jurczak, P. Absil, S. Biesemans, and T. Hoffmann, "Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10 ps invertor delay," in VLSI Symp. Tech. Dig., Jun. 2008, pp. 130-131.
-
-
-
-
15
-
-
50349099176
-
Tuning PMOS Mo(O,N) metal gates to NMOS by addition of DyO capping layer
-
Dec
-
J. Petry, R. Singanamalla, K. Xiong, C. Ravit, E. Simoen, R. O'Connor, A. Veloso, C. Adelmann, S. Van Elshocht, V. Paraschiv, S. Brus, J. Van Berkum, S. Kubicek, K. DeMeyer, S. Biesemans, and J.C. Hooker, "Tuning PMOS Mo(O,N) metal gates to NMOS by addition of DyO capping layer," in IEDM Tech. Dig., Dec. 2007, pp. 329-332.
-
(2007)
IEDM Tech. Dig
, pp. 329-332
-
-
Petry, J.1
Singanamalla, R.2
Xiong, K.3
Ravit, C.4
Simoen, E.5
O'Connor, R.6
Veloso, A.7
Adelmann, C.8
Van Elshocht, S.9
Paraschiv, V.10
Brus, S.11
Van Berkum, J.12
Kubicek, S.13
DeMeyer, K.14
Biesemans, S.15
Hooker, J.C.16
-
16
-
-
62249119894
-
3 incorporation and stack variation
-
Oct
-
3 incorporation and stack variation," Jpn. J. Appl. Phys., vol. 47, no. 10, pp. 7780-7783, Oct. 2008.
-
(2008)
Jpn. J. Appl. Phys
, vol.47
, Issue.10
, pp. 7780-7783
-
-
Mise, N.1
Kadoshima, M.2
Morooka, T.3
Eimori, T.4
Nara, Y.5
Ohji, Y.6
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