Tuning PMOS Mo(O,N) metal gates to NMOS by addition of DyO capping layer

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2007, Pages 329-332

  Petry, J ^a   Singanamalla, R ^b,c   Xiong, K ^a   Ravit, C ^a   Simoen, E ^b   O'Connor, R ^b   Veloso, A ^b   Adelmann, C ^b   Van Elshocht, S ^b   Paraschiv, V ^b   Brus, S ^b   Van Berkum, J ^d   Kubicek, S ^b   De Meyer, K ^b,c   Biesemans, S ^b   Hooker, J C ^a  

^a NXP TSMC Research Center   (Belgium)

^b CMOS Device Research Group   (Belgium)

^c UNIVERSITY OF LEUVEN   (Belgium)

^d PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CONDUCTIVITY; ELECTRON MOBILITY; MOLYBDENUM; SILICON;

CAPPING LAYER; CONDUCTION BANDS; METAL GATES;

ELECTRON DEVICES;

EID: 50349099176     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4418938     Document Type: Conference Paper

References (6)

1. R. Singanamalla et al. IEDM tech. dig., 2006.
2. L.-Å. Ragnarsson et al., IEEE Elec.Dev.Let., 28 (6), June 2007.
3. C. Adelmann et al., Chem. Vap. Deposition (in print, 2007).
4. H.Y. Yu et al., VLSI tech.dig., 2006.
5. E. Simoen and C. Claeys, Solid-State Electron.43, p.865-882, May 1999.
6. V.S.Chang et al., to be published in EDL.