Time-dependent behaviour of full open defects in interconnect lines

Proceedings - International Test Conference

Volumn , Issue , 2008, Pages

  Rodriguez Montanes R ^a   Arumi D ^a   Figueras, J ^a   Eichenberger, S ^b   Hora, C ^b   Kruseman, B ^b  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

BROKEN WIRES; DEFECTIVE CIRCUITS; EXPERIMENTAL EVIDENCE; FUTURE TECHNOLOGIES; GATE OXIDE THICKNESS; GATE TUNNELLING; INTERCONNECT LINES; M-TECHNOLOGIES; NANOMETER CMOS; NANOMETER TECHNOLOGY; PARASITIC CAPACITANCE; QUIESCENT STATE; TEST CHIPS; TIME-DEPENDENT BEHAVIOUR; TRANSIENT EVOLUTION; TRANSIENT RESPONSE; TRAPPED CHARGE;

DELAY CIRCUITS; ELECTRON TUNNELING; LEAKAGE (FLUID); TUNNELING (EXCAVATION);

TECHNOLOGY;

EID: 67249104053     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2008.4700575     Document Type: Conference Paper

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