IDDQ testing of single floating gate defects using a two-pattern vector

Electronics Letters

Volumn 32, Issue 17, 1996, Pages 1572-1574

  Champac, V H ^a   Figueras, J ^b  

^a INSTITUTO NACIONAL DE ASTROFÍSICA   (Mexico)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

Integrated circuit testing; Testing

Indexed keywords

ELECTRIC CURRENT MEASUREMENT; ELECTRIC NETWORK ANALYSIS; SEMICONDUCTOR DEVICE MODELS; TRANSISTORS; VECTORS;

SINGLE FLOATING GATE DEFECTS; TWO PATTERN VECTORS;

INTEGRATED CIRCUIT TESTING;

EID: 0030217085     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19961033     Document Type: Article

References (6)

1. RENOVELL, M., and CAMBON, G.: 'Topology dependence of floating gate faults in MOS circuits', Electron. Lett., 1986, 22, (3), pp. 152-153
2. MALY, W., NAG, P.K., and NIGH, P.: 'Testing oriented analysis of CMOS ICs with opens'. Proc. Int. Conf. Computer-Aided Design, 1988, pp. 344-347
3. DDQ testing', IEEE Trans., 1994, CAD-13, (3), pp. 359-369
4. JOHNSON, S.: 'Residual charge on the faulty floating gate MOS transistors',Int. Test Conf., 1994, pp. 555-561
5. DDQ Testing of CMOS opens: An experimental study. Int. Test Conf., 1995, pp. 479-489
6. HAWKINS, C.F., SODEN, J.M., RICHTER, A.W., and FERGUSON, F.J.: 'Defect classes - An overdue paradigm for CMOS IC testing'. Int. Test Conf., 1994, pp. 413-425