Diagnosis of full open defects in interconnecting lines

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2007, Pages 158-163

  Rodriguez Montanes, R ^a   Arumi D ^a   Figueras, J ^a   Einchenberger, S ^b   Hora, C ^b   Kruseman, B ^b   Lousberg, M ^b   Majhi, A K ^b  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

CMOS; Defect diagnosis; Full open defect; Interconnecting line

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRIC POWER UTILIZATION; TOPOLOGY;

DEFECT DIAGNOSIS; INTERCONNECTING LINE;

INTERCONNECTION NETWORKS;

EID: 35148837943     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2007.28     Document Type: Conference Paper

References (23)

1. Hawkins, C.F.; Soden, J.M.; Righter, A.W.; Ferguson, F.J.; "Defect classes-an overdue paradigm for CMOS IC testing", Proceedings of the International Test Conference, pp.413-425, 1994.
2. Needham, W.; Prunty, C.; Eng Hong Yeoh; "High volume microprocessor test escapes, an analysis of defects our tests are missing", Proceedings of the International Test Conference, pp.25-34, 1998.
3. R. Rodríguez-Montañés, P. Volf and J. Pineda de Gyvez, "Resistance characterization for weak open defects", IEEE Design & Test of Computers, Vol. 19, N.5, pp.18-26, 2002.
4. M. Renovell, G. Cambon, "Topology Dependence of Floating Gate Faults in MOS Integrated Circuits," Electronics Letters, Vol. 22, No. 3, pp. 152-153, 1986.
5. C.L. Henderson, J.M. Soden and C.F. Hawkins, "The Behavior and Testing Implications of CMOS IC Open Circuits", Proceedings of the International Test Conference, pp.302-3, 1991.
6. H. Sue, C. Di and J.A.G. Jess, "Probability analysis for CMOS floating gate faults", Proceedings of the European Design and Test Conference, pp. 443-448, 1994.
7. H. Konuk, "Voltage and current-based fault simulation for interconnect open defects", IEEE Transactions on Computed Aided Design of integrated circuits and systems, Volume 18, Number 12, pp. 1768-1779, 1999.
8. U. Choudhury, A. Sangiovanni-Vincentelli, "Automatic generation of analytical models for interconnect capacitances", Transactions on Computed Aided Design of Integrated Circuits and Systems, Vol. 14, Is: 4, pp. 470-480, 1995.
9. Champac, V.H; Rubio, A.; Figueras, J., "Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing", Transactions on Computed Aided Design of Integrated Circuits and Syst, Vol. 13, Is 3, pp.359-369, 1994.
10. Konuk, H.; Ferguson, F.J.;, "An unexpected factor in testing for CMOS opens: the die surface", Proceedings of the VLSI Test Symposium, pp. 422-429, 1996.
11. S. Johnson, "Residual charge on the faulty floating gate CMOS transistor", Proceedings of the International Test Conference, pp. 555-561, 1994.
12. Rafiq, S.; Ivanov, A.; Tabatabaei, S.; Renovell, M.; "Testing for floating gates defects in CMOS circuits", Proceedings of the Asian Test Sympos., pp.228-236, 1998.
13. Lavo, D.B.; Larrabee, T.; Chess, B.; "Beyond the byzantine generals: unexpected behavior and bridging fault diagnosis", Proceedings of the International Test Conference, pp. 611-619, 1996.
14. Venkataraman, S.; Drummonds, S.B.; "Poirot: applications of a logic fault diagnosis tool", IEEE Design & Test of Computers, Vol 18, Is. 1, Jan.-Feb. pp.19-30, 2001.
15. Bartenstein, T.; Heaberlin, D.; Huisman, L.; Sliwinski, D.; "Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm", Proceedings of the International Test Conference,. pp.287-296, 2001.
16. Zhiyuan Wang; Marek-Sadowska, M.; Tsai, K.-H.; Rajski, J.;, "Analysis and methodology for multiple-fault diagnosis", IEEE Transactions on Computed Aided Design of Integr Circuits and Syst, Vol 25, Is 3, pp.558-575, 2006.
17. Lavo, D.B.; Hartanto, I.; Larrabee, T.; "Multiplets, models, and the search for meaning: improving per-test fault diagnosis", Proceedings of the International Test Conference, pp.250-259, 2002.
18. Shi-Yu Huang; "Diagnosis of Byzantine open-segment faults [scan testing]", Proceedings of the Asian Test Symposium, pp.248-253, 2002.
19. Sato, Y.; Yamazaki, L.; Yamanaka, H.; Ikeda, T.; Takakura, M.;, 'A Persistent Diagnostic Technique for Unstable Defects', Proceedings of the International Test Conference, pp.242-249, 2002.
20. Chem, J.-H.; Huang, J.; Arledge, L.; Li, P.-C.; Yang, P.; 'Multilevel metal capacitance models for CAD design synthesis systems', Electron Device Letters, Vol 13, Is 1, pp.32-34, 1992.
21. Johnson, S.;, "Residual charge on the faulty floating gate CMOS transistor", Proceedings of the International Test Conference, pp. 555-561, 1994.
22. "Faloc Reference Manual 3.9", NXP Semiconductors, 2004.
23. C. Hora, "On Diagnosing Faults in Digital Circuits", PhD. dissertation, Technische Universiteit Eindhoven, 2002.