Full open defects in nanometric CMOS

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2008, Pages 119-124

  Arumi D ^a   Rodriguez Montanes R ^a   Figueras, J ^a   Eichenberger, S ^b   Hora, C ^b   Kruseman, B ^b  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER NETWORKS; DIGITAL SIGNAL PROCESSING; ELECTRON TUNNELING; TUNNELING (EXCAVATION);

GATE TUNNELLING; NANOMETRIC; VLSI TESTS;

TECHNOLOGY;

EID: 51449087363     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2008.31     Document Type: Conference Paper

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