32 NM Logic patterning options with immersion lithography

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6924, Issue , 2008, Pages

  Lai, K ^a   Burns, S ^a   Halle, S ^a   Zhuang, L ^a   Colburn, M ^a   Allen, S ^a   Babeock, C ^b   Baum, Z ^a   Burkhardt, M ^a   Dai, V ^b   Dunn, D ^a   Geiss, E ^b   Haffner, H ^c   Han, G ^a   Lawson, P ^a   Mansfield, S ^a   Meiring, J ^a   Morgenfeld, B ^a   Tabery, C ^b   Zou, Y ^b   Sarma, C ^c   Tsou, L ^a   Yan, W ^a   Zhuang, H ^c   Gil, D ^a   Medeiros, D ^a   more..

^a IBM   (United States)

^b ADVANCED MICRO DEVICES   (United States)

^c INFINEON TECHNOLOGIES   (United States)

Author keywords

193nm lithography; Double dipole lithography; Double patterning; Immersion lithography; Logic patterning; Pattern splitting; Pitch splitting; Printing assist features

Indexed keywords

(E ,3E) PROCESS; 2D IMAGING; ALLIANCE (CO); DOUBLE EXPOSURE; DOUBLE PATTERNING; EUV LITHOGRAPHY (EUVL); HIGH INDEX; ILLUMINATION CONDITIONS; IMAGING PROPERTIES; IMMERSION LITHOGRAPHY (IML); INNOVATIVE PROCESSES; LINE ENDS; LINE-WIDTH CONTROL; LOGIC CONSTRUCTS; MULTIPLE EXPOSURES; NODE DEVELOPMENT; OPTICAL MICRO LITHOGRAPHY; RAYLEIGH; RESIST FILMS; SCALING LIMITS; SEMICONDUCTOR INDUSTRIES; TECHNICAL CHALLENGES; THROUGH-MASK; TRANSITION (JEL CLASSIFICATIONS:E52 ,E41 ,E31);

AEROSPACE APPLICATIONS; ARCHITECTURAL DESIGN; COMPUTER NETWORKS; CURVE FITTING; FUZZY LOGIC; INDUSTRY; MICROFLUIDICS; OPTICAL SYSTEMS; OPTICS; OPTIMIZATION; PROCESS DESIGN; PROCESS ENGINEERING; SEMICONDUCTOR DEVICE MANUFACTURE; SODIUM; TECHNOLOGY;

LITHOGRAPHY;

EID: 45449117473     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.784107     Document Type: Conference Paper

References (8)

1. K. Mistry et al., "A 45nm Logic Technology with High-k + Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging", IEDM Tech Dig., pp 247-250, (2007). Y. Borodovsky, "Marching to the Beat of Moorse's Law", SPIE Microlithogaphy, 2006.
2. J. Meiring, H. Haffner, C. Fonseca, S. Halle, and S. Mansfield: "ACLV Driven Double-Patterning Decomposition With Extensively Added Printing Assist Features (PrAFs)", Proc. SPIE Vol. 6520 (SPIE, Bellingham, WA, 65201U (2007).
3. H. Haffner, J. Meiring, Z. Baum, S. Halle: "Paving the way to a full chip gate level double patterning application", Proc. SPIE Vol. 6730 (SPIE, Bellingham, WA, 67302C ( 2007).
4. H. Haffner, J. Meiring, Z. Baum, S. Halle, and S. Mansfield, "Solving the gate level ACLV challenge with double patterning and printing assist features", Microlithography World, in press.
5. J. E. Meiring et al, "ACLV driven double-patterning decomposition with extensively added printing assist features (PrAFs)" Proceedings of the SPIE, Volume 6520, pp. 65201U (2007).
6. M. Burkhardt, et al, "Dark field double dipóle lithography (DDL) for back-end-of-line processes" Proceedings of SPIE, 6520, pp. 65200K (2007)
7. Matrix OPC is a trademark of Mentor Graphics Inc.
8. B. Arnold, M. Dusa, J. Finders, et al ," Metrology challenges of double exposure and double patterning", Proceedings of SPIE, 6518, pp. 651902 (2007)