Limited bandwidth to affect processor design

IEEE Micro

Volumn 17, Issue 6, 1997, Pages 55-62

  Burger, Doug ^a,b,c,d   Goodman, James R ^a,d,e   Kägi, Alain ^a,f  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

^b YALE UNIVERSITY   (United States)

^c IEEE   (United States)

^d University of Wisconsin Madison   (United States)

^e UNIVERSITY OF CALIFORNIA   (United States)

^f ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL STORAGE; SEMICONDUCTOR STORAGE;

BENCHMARKS; DRAM; DYNAMIC RANDOM ACCESS MEMORY;

RANDOM ACCESS STORAGE;

EID: 0031277174     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.641597     Document Type: Article

References (12)

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2. G.S. Sohi, S.E. Breach, and T.N. Vijaykumar, "Multiscalar Processors," Proc. 22nd Ann. Int'/Symp. Computer Architecture, ACM, 1995, pp. 414-425.
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