-
1
-
-
0032647363
-
A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOS register file
-
Hwang, W., Joshi, R. V., and Henkels, W. H. A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOS register file. IEEE Journal of Solid-State Circuits, 1999, pp. 56-67.
-
(1999)
IEEE Journal of Solid-State Circuits
, pp. 56-67
-
-
Hwang, W.1
Joshi, R.V.2
Henkels, W.H.3
-
2
-
-
4544274990
-
On circuit techniques to improve noise immunity of CMOS dynamic logic
-
Li, D., and Mazumder, P. On circuit techniques to improve noise immunity of CMOS dynamic logic. Very Large Scale Integration (VLSI) Systems, 2004, pp. 910-925.
-
(2004)
Very Large Scale Integration (VLSI) Systems
, pp. 910-925
-
-
Li, D.1
Mazumder, P.2
-
3
-
-
0033652346
-
Reliable low-power design in the presence of deep submicron noise
-
Shanbhag, N., Soumyanath, K., and Martin, S. Reliable low-power design in the presence of deep submicron noise. ISLPED, 2000, pp. 295-302.
-
(2000)
ISLPED
, pp. 295-302
-
-
Shanbhag, N.1
Soumyanath, K.2
Martin, S.3
-
4
-
-
0041633858
-
-
DAC
-
Borkar, S., Karnik, T., Narendra, S., Tschanz, J., Keshavarzi, A., and De, V. Parameter variations and impact on circuits and microarchitecture. DAC, 2003, pp. 338-342.
-
(2003)
Parameter variations and impact on circuits and microarchitecture
, pp. 338-342
-
-
Borkar, S.1
Karnik, T.2
Narendra, S.3
Tschanz, J.4
Keshavarzi, A.5
De, V.6
-
5
-
-
0034784945
-
A 0.13 μm 6 GHz 256×32b leakage-tolerant register file
-
Krishnamurthy, R., Alvandpour, A., Balamurugan, G., Shanbhagh, N., Soumyanath, K., and Borkar, S. A 0.13 μm 6 GHz 256×32b leakage-tolerant register file. VLSI Circuits, 2001, pp. 25-26.
-
(2001)
VLSI Circuits
, pp. 25-26
-
-
Krishnamurthy, R.1
Alvandpour, A.2
Balamurugan, G.3
Shanbhagh, N.4
Soumyanath, K.5
Borkar, S.6
-
6
-
-
0030086605
-
A 0.9 V 150 MHz 10 mW 4 mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme
-
Kuroda, T., Fujita, T., Mita, S., Nagamatu, T., Yoshioka, S., Sano, F., Norishima, M., Murota, M., Kako, M., Kinugawa, M., Kakumu, M., and Sakurai, T. A 0.9 V 150 MHz 10 mW 4 mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme. ISSCC, 1996, pp. 166-167.
-
(1996)
ISSCC
, pp. 166-167
-
-
Kuroda, T.1
Fujita, T.2
Mita, S.3
Nagamatu, T.4
Yoshioka, S.5
Sano, F.6
Norishima, M.7
Murota, M.8
Kako, M.9
Kinugawa, M.10
Kakumu, M.11
Sakurai, T.12
-
7
-
-
33745484581
-
Self calibrating circuit design for variation tolerant VLSI systems
-
Kim, C. H., Hsu, S., Krishnamurthy, R., Borkar, S., and Roy, K. Self calibrating circuit design for variation tolerant VLSI systems. On-Line Testing Symposium, 2005, pp. 100-105.
-
(2005)
On-Line Testing Symposium
, pp. 100-105
-
-
Kim, C.H.1
Hsu, S.2
Krishnamurthy, R.3
Borkar, S.4
Roy, K.5
-
8
-
-
0034794938
-
A conditional keeper technique for sub-0.13p wide dynamic gates
-
Alvandpour, A., Krishnamurthy, R., Soumyanath, K., Borkar, S. A conditional keeper technique for sub-0.13p wide dynamic gates. VLSI Circuits, 2001, pp. 29-30.
-
(2001)
VLSI Circuits
, pp. 29-30
-
-
Alvandpour, A.1
Krishnamurthy, R.2
Soumyanath, K.3
Borkar, S.4
-
9
-
-
0036474722
-
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
-
Bowman, K., Duval, S.G., and Meindl, J.D. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. IEEE Journal of Solid-state Circuits, 2002, pp.183-190.
-
(2002)
IEEE Journal of Solid-state Circuits
, pp. 183-190
-
-
Bowman, K.1
Duval, S.G.2
Meindl, J.D.3
-
10
-
-
0032203877
-
A process-independent, 800-MB/s, DRAM byte-wide interface featuring command interleaving and concurrent memory operation
-
Griffin, M.M., Zerbe, J., Tsang, G., Ching, M., and Portmann, C.L., A process-independent, 800-MB/s, DRAM byte-wide interface featuring command interleaving and concurrent memory operation. Journal of Solid-State Circuits, IEEE, 1998, pp. 1741-1751.
-
(1998)
Journal of Solid-State Circuits, IEEE
, pp. 1741-1751
-
-
Griffin, M.M.1
Zerbe, J.2
Tsang, G.3
Ching, M.4
Portmann, C.L.5
-
11
-
-
0003514380
-
-
Cambridge University Press, New York, NY
-
Taur, Y., and Ning, T.H. Fundamentals of Modern VLSI Devices. Cambridge University Press, New York, NY, 1998.
-
(1998)
Fundamentals of Modern VLSI Devices
-
-
Taur, Y.1
Ning, T.H.2
-
12
-
-
85165840247
-
-
http://www-device.eecs.berkeley.edu/~ptm/mosfet.html.
-
-
-
-
13
-
-
0034429814
-
Delay variability: Sources, impacts and trends
-
Nassif, S. Delay variability: sources, impacts and trends. ISSCC, 2000, pp. 368-369.
-
(2000)
ISSCC
, pp. 368-369
-
-
Nassif, S.1
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