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Volumn , Issue , 2006, Pages 977-982

A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates

Author keywords

Dynamic gates; Keeper design; Low power design; Process variation; Reliability; Robustness; VLSI

Indexed keywords

COMPUTER SIMULATION; ELECTRIC POWER UTILIZATION; LEAKAGE CURRENTS; MOS DEVICES; NETWORKS (CIRCUITS); THRESHOLD VOLTAGE;

EID: 34547145395     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1147156     Document Type: Conference Paper
Times cited : (12)

References (13)
  • 1
  • 2
    • 4544274990 scopus 로고    scopus 로고
    • On circuit techniques to improve noise immunity of CMOS dynamic logic
    • Li, D., and Mazumder, P. On circuit techniques to improve noise immunity of CMOS dynamic logic. Very Large Scale Integration (VLSI) Systems, 2004, pp. 910-925.
    • (2004) Very Large Scale Integration (VLSI) Systems , pp. 910-925
    • Li, D.1    Mazumder, P.2
  • 3
    • 0033652346 scopus 로고    scopus 로고
    • Reliable low-power design in the presence of deep submicron noise
    • Shanbhag, N., Soumyanath, K., and Martin, S. Reliable low-power design in the presence of deep submicron noise. ISLPED, 2000, pp. 295-302.
    • (2000) ISLPED , pp. 295-302
    • Shanbhag, N.1    Soumyanath, K.2    Martin, S.3
  • 9
    • 0036474722 scopus 로고    scopus 로고
    • Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
    • Bowman, K., Duval, S.G., and Meindl, J.D. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. IEEE Journal of Solid-state Circuits, 2002, pp.183-190.
    • (2002) IEEE Journal of Solid-state Circuits , pp. 183-190
    • Bowman, K.1    Duval, S.G.2    Meindl, J.D.3
  • 10
    • 0032203877 scopus 로고    scopus 로고
    • A process-independent, 800-MB/s, DRAM byte-wide interface featuring command interleaving and concurrent memory operation
    • Griffin, M.M., Zerbe, J., Tsang, G., Ching, M., and Portmann, C.L., A process-independent, 800-MB/s, DRAM byte-wide interface featuring command interleaving and concurrent memory operation. Journal of Solid-State Circuits, IEEE, 1998, pp. 1741-1751.
    • (1998) Journal of Solid-State Circuits, IEEE , pp. 1741-1751
    • Griffin, M.M.1    Zerbe, J.2    Tsang, G.3    Ching, M.4    Portmann, C.L.5
  • 12
    • 85165840247 scopus 로고    scopus 로고
    • http://www-device.eecs.berkeley.edu/~ptm/mosfet.html.
  • 13
    • 0034429814 scopus 로고    scopus 로고
    • Delay variability: Sources, impacts and trends
    • Nassif, S. Delay variability: sources, impacts and trends. ISSCC, 2000, pp. 368-369.
    • (2000) ISSCC , pp. 368-369
    • Nassif, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.