An 800MHz embedded DRAM with a concurrent refresh mode

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Kirihata, Toshiaki ^a   Parries, Paul ^a   Hanson, David ^a   Kim, Hoki ^a   Golz, John ^a   Fredeman, Gregory ^a   Rajeevakumar, Raj ^a   Griesemer, John ^a   Robson, Norman ^a   Cestero, Alberto ^a   Wordeman, Matt ^a   Iyer, Subramanian ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANK SELECT SIGNAL (BSEL); COMMAND MULTIPLIERS; LOGIC ARRAY DEVICES; MEMORY ACCESS;

CAPACITORS; COMPUTER SIMULATION; DATA REDUCTION; ELECTRIC POTENTIAL; EMBEDDED SYSTEMS; GATES (TRANSISTOR);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 2442642602     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. J. Barth et. al., "A 300MHz Multi-Banked eDRAM Macro Featuring GND Sense Bitline Twisting and Direct Reference Cell Write," ISSCC Dig. Tech. Papers, pp.156-157, Feb. 2002.
2. C. Hwang et. al., "A 2.9ns Random Access Cycle Embedded DRAM with a Destructive-Read Architecture," Symp. on VLSI Circuits Dig., pp. 174-175, Jun. 2002.