A 500MHz random cycle 1.5ns-latency, SOI embedded DRAM macro featuring a 3T micro sense amplifier

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 486-488

  Barth, John ^a   Reohr, William ^b   Parries, Paul ^a   Fredeman, Greg ^a   Golz, John ^a   Schuster, Stanley ^b   Matick, Richard ^b   Hunter, Hillery ^b   Tanner III, Charles ^a   Harig, Joseph ^a   Kim, Hoki ^a   Khan, Babar ^a   Griesemer, John ^a   Havreluk, Robert ^b   Yanagisawa, Kenji ^a   Kirihata, Toshiaki ^a   Iyer, Subramanian ^a  

^a IBM   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; POWER AMPLIFIERS; RANDOM PROCESSES; VOLTAGE CONTROL;

DEEP-TRENCH DRAM PROCESSES; HIGH-PERFORMANCE MICROPROCESSORS; MICRO SENSE AMPLIFIERS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 34548851167     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373506     Document Type: Conference Paper

References (10)

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