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Volumn , Issue , 2008, Pages 66-69

An on-chip dual supply charge pump system for 45nm PD SOI eDRAM

Author keywords

EDRAM; SOI; Switched capacitor circuits

Indexed keywords

APPLICATIONS.; CHARGE PUMPS; CLOCK CIRCUITS; DC LOADS; DUAL SUPPLIES; DUAL SUPPLY SYSTEMS; EDRAM; ON CHIPS; SOI; SWITCHED CAPACITOR CIRCUITS; SWITCHED CAPACITORS; SYSTEM SUPPORTS; TURN OFFS; WORD LINES;

EID: 58049110447     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2008.4681793     Document Type: Conference Paper
Times cited : (8)

References (8)
  • 1
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    • A 500MHz random cycle, 1.5ns-latency, SOI embedded DRAM macro featuring a three-transistor sense amplifier
    • J. Barth, et al, "A 500MHz random cycle, 1.5ns-latency, SOI embedded DRAM macro featuring a three-transistor sense amplifier," ISSCC Dig. Tech. Papers, pp. 486-487, 2007.
    • (2007) ISSCC Dig. Tech. Papers , pp. 486-487
    • Barth, J.1
  • 2
    • 58049109894 scopus 로고    scopus 로고
    • 2 high performance 65nm SOI based embedded DRAM for on-processor applications, in IEDM Tech. Dig., 2006.
    • 2 high performance 65nm SOI based embedded DRAM for on-processor applications, in IEDM Tech. Dig., 2006.
  • 3
    • 0026138627 scopus 로고
    • An experimental 1.5-V 64-Mb DRAM
    • Y. Nakagome, et al., "An experimental 1.5-V 64-Mb DRAM," IEEE J. Solid-States Circuits, vol. 26, no. 4, pp. 465-472, 1991.
    • (1991) IEEE J. Solid-States Circuits , vol.26 , Issue.4 , pp. 465-472
    • Nakagome, Y.1
  • 4
    • 0028123971 scopus 로고
    • A 10-bit 20 MS/s 35 mW pipeline A/D converter
    • T. Cho and P. Gray, "A 10-bit 20 MS/s 35 mW pipeline A/D converter," Proc. CICC, pp. 499-502, 1994.
    • (1994) Proc. CICC , pp. 499-502
    • Cho, T.1    Gray, P.2
  • 5
    • 0032028335 scopus 로고    scopus 로고
    • A high-efficiency CMOS voltage doubler
    • P. Favrat, et al, "A high-efficiency CMOS voltage doubler," IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 410-416, 1998.
    • (1998) IEEE J. Solid-State Circuits , vol.33 , Issue.3 , pp. 410-416
    • Favrat, P.1
  • 6
    • 18444416788 scopus 로고    scopus 로고
    • Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doubler
    • H. Lee and P. Mok, "Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doubler," IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1136-1146, 2005.
    • (2005) IEEE J. Solid-State Circuits , vol.40 , Issue.5 , pp. 1136-1146
    • Lee, H.1    Mok, P.2
  • 7
    • 58049132808 scopus 로고    scopus 로고
    • A one MB cache system prototype with 2GHz embedded DRAMs in 45nm SOI CMOS
    • P. Klim, et al, "A one MB cache system prototype with 2GHz embedded DRAMs in 45nm SOI CMOS," Symp. VLSI Circuits, 2007.
    • (2007) Symp. VLSI Circuits
    • Klim, P.1
  • 8
    • 49549084181 scopus 로고    scopus 로고
    • G. Uhlmann, et al., A commercial field programmable dense eFUSE array memory with 99.999% sense yield for 45nm SOI CMOS, ISSCC Dig. Tech. Papers, 2008.
    • G. Uhlmann, et al., "A commercial field programmable dense eFUSE array memory with 99.999% sense yield for 45nm SOI CMOS, ISSCC Dig. Tech. Papers, 2008.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.