2GHz 2Mb 2T gain-cell memory macro with 128GB/S bandwidth in a 65nm logic process

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 273-275

  Somasekhar, Dinesh ^a   Ye, Yibin ^a   Aseron, Paolo ^a   Lu, Shih Lien ^a   Khellah, Muhammad ^a   Howard, Jason ^a   Ruhl, Greg ^a   Karnik, Tanay ^a   Borkar, Shekhar Y ^a   De, Vivek ^a   Keshavarzi, Ali ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; STATIC RANDOM ACCESS STORAGE;

BIT LINES; CYCLE TIME; LOGIC PROCESS; MACRO FEATURES; NONDESTRUCTIVE READ-OUT; PIPELINED ARCHITECTURE; PRE-CHARGE; REFRESH TIME;

COMPUTER CIRCUITS;

EID: 49549124780     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523163     Document Type: Conference Paper

References (7)

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5. 2 SRAM Cell," IEDM Dig. Tech. Papers, pp. 657-660, Dec. 2004.
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7. Y. Wang, et al., "A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications," ISSCC Dig. Tech. Papers, pp. 324-325, Feb. 2007.