A 14b 100MS/S pipelined ADC with a merged active S/H and first MDAC

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 248-250

  Lee, Byung Geun ^a   Min, Byung Moo ^b   Manganaro, Gabriele ^b   Valvano, Jonathan W ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; DUAL GATE OXIDE; LOW-POWER OPERATION; PIPELINED ADCS;

PIPELINES;

EID: 49549085307     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523150     Document Type: Conference Paper

References (4)

1. B. M. Min, P. Kim, D. Boisvert, A. Aude, "A 69mW 10b 80MS/s Pipelined CMOS ADC, " ISSCC Dig. Tech. Papers, pp. 324-325, Feb. 2003.
2. I. Mebr, L. Singer, "A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC," IEEE J. Solid-State Circuits, vol. 35, no. 3, pp.318-325, Mar. 2000.
3. M. Yoshioka, M. Kudo, K. Gotoh, Y. Watanabe, "A 10b 125MS/s 40mW Pipelined ADC in 0.18μm CMOS," ISSCC Dig. Tech. Papers, pp. 282-283, Feb. 2005.
4. 2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 456-457, Feb. 2007.