A 1.2V 250mW 14b 100MS/s digitally calibrated pipeline ADC in 90nm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2008, Pages 74-75

  Van De Vel, Hans ^a   Buter, Berry ^a   Van Der Ploeg, Hendrik ^a,b   Vertregt, Maarten ^a   Geelen, Govert ^a   Paulus, Edward ^a  

^a NXP SEMICONDUCTORS   (Netherlands)

^b Catena Radio Design   (Netherlands)

Author keywords

A D conversion; Deep submicron CMOS and low supply voltage; Digital calibration; Pipeline ADC

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CALIBRATION; CMOS INTEGRATED CIRCUITS; VLSI CIRCUITS;

A/D CONVERSION; DEEP-SUBMICRON CMOS AND LOW SUPPLY VOLTAGE; DIGITAL BACKGROUND CALIBRATION; DIGITAL CALIBRATIONS; ENABLING TECHNIQUES; INPUT FREQUENCY; PIPELINE ADCS; PIPELINE STAGES;

PIPELINES;

EID: 51949117771     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2008.4585957     Document Type: Conference Paper

References (5)

1. P. Bogner et al., "A 14b 100MS/s digitally self-calibrated pipelined ADC in 0.13μm CMOS," ISSCC Dig. Tech. Papers, pp. 224-225, Feb. 2006.
2. G. Geelen, E. Paulus, D. Simanjuntak, H. Pastoor and R. Verlinden, "A 90nm CMOS 1.2V 10b power and speed programmable pipelined ADC with 0.5pJ/conversion-step," ISSCC Dig. Tech. Papers, pp. 214-215, Feb. 2006.
3. B. Murmann and B. E. Boser, "A 12b 75MS/s pipelined ADC using open-loop residue amplification," ISSCC Dig. Tech. Papers, pp. 328-329, Feb. 2003.
4. H. van der Ploeg and B. Nauta, Calibration Techniques in Nyquist A/D Converters, Springer, 2006.
5. D. Kelly, W. Yang, I. Mehr, M. Sayuk and L. Singer, "A 3V 340mW 14b 75MSPS CMOS ADC with 85dB SFDR at Nyquist," ISSCC Dig. Tech. Papers, pp. 143-144, Feb. 2001.