-
1
-
-
27644469931
-
Automatic and hardware-efficient SoC integration by qos network on chip
-
Tel Aviv
-
Bolotin, E., Morgenshtein, A., Cidon, I., Kolodny, A.: Automatic and hardware-efficient SoC integration by qos network on chip. In: IEEE International Conference on Electronics, Circuits and Systems, Tel Aviv (2004)
-
(2004)
IEEE International Conference on Electronics, Circuits and Systems
-
-
Bolotin, E.1
Morgenshtein, A.2
Cidon, I.3
Kolodny, A.4
-
2
-
-
0034848112
-
Route packets, not wires: On-chip interconnection networks
-
Las Vegas, Nevada, USA
-
Dally, W.J., Towles, B.: Route packets, not wires: On-chip interconnection networks. In: Design Automation Conference, Las Vegas, Nevada, USA (2001) 684-689
-
(2001)
Design Automation Conference
, pp. 684-689
-
-
Dally, W.J.1
Towles, B.2
-
3
-
-
84893687806
-
A generic architecture for on-chip packet-switched interconnections
-
Paris, France
-
Guerrier, P., Greiner, A.: A generic architecture for on-chip packet-switched interconnections. In: Design Automation and Test in Europe, Paris, France (2000) 250-256
-
(2000)
Design Automation and Test in Europe
, pp. 250-256
-
-
Guerrier, P.1
Greiner, A.2
-
6
-
-
33847226618
-
Design issues and performance evaluation of mesh NoC with regions
-
Oulu, Finland
-
Holsmark, R., Kumar, S.: Design issues and performance evaluation of mesh NoC with regions. In: IEEE Norchip, Oulu, Finland (2005) 40-43
-
(2005)
IEEE Norchip
, pp. 40-43
-
-
Holsmark, R.1
Kumar, S.2
-
7
-
-
0027837827
-
A new theory of deadlock-free adaptive routing in wormhole networks
-
Duato, J.: A new theory of deadlock-free adaptive routing in wormhole networks. IEEE Transactions on Parallel and Distribuited Systems 4 (1993) 1320-1331
-
(1993)
IEEE Transactions on Parallel and Distribuited Systems
, vol.4
, pp. 1320-1331
-
-
Duato, J.1
-
8
-
-
33746738613
-
APSRA: A methodology for design of application specific routing algorithms for NoC systems
-
Dip. di Ingegneria Informatica e delle Telecomunicazioni, Univ. di Catania
-
Palesi, M., Holsmark, R., Kumar, S., Catania, V.: APSRA: A methodology for design of application specific routing algorithms for NoC systems. Technical Report DIIT-TR-01060406, Dip. di Ingegneria Informatica e delle Telecomunicazioni, Univ. di Catania (2006)
-
(2006)
Technical Report
, vol.DIIT-TR-01060406
-
-
Palesi, M.1
Holsmark, R.2
Kumar, S.3
Catania, V.4
-
9
-
-
33746670413
-
Asynchronous network node design for network-on-chip
-
Wang, X., Siguenza-Tortosa, D., Ahonen, T., Nurmi, J.: Asynchronous network node design for network-on-chip. In: International Symposium on Signals, Circuits and Systems. Volume 1. (2005) 55-58
-
(2005)
International Symposium on Signals, Circuits and Systems
, vol.1
, pp. 55-58
-
-
Wang, X.1
Siguenza-Tortosa, D.2
Ahonen, T.3
Nurmi, J.4
-
10
-
-
0032761270
-
LAPSES: A recipe for high performance adaptive router design
-
Orlando, Florida, USA
-
Vaidya, A.S., Sivasubramaniam, A., Das, C.R.: LAPSES: A recipe for high performance adaptive router design. In: Fifth International Symposium On High-Performance Computer Architecture, Orlando, Florida, USA (1999) 236-243
-
(1999)
Fifth International Symposium on High-performance Computer Architecture
, pp. 236-243
-
-
Vaidya, A.S.1
Sivasubramaniam, A.2
Das, C.R.3
|