A 14b low-power pipeline A/D converter using a pre-charging technique

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 196-197

  Honda, Kazutaka ^a   Liu, Zheng ^a   Furuta, Masanori ^a   Kawahito, Shoji ^a  

^a SHIZUOKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; SOFTWARE PROTOTYPING;

BIT PIPELINES; PRECHARGING TECHNIQUES;

ANALOG TO DIGITAL CONVERSION;

EID: 39749179880     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342712     Document Type: Conference Paper

References (3)

1. K. Iizuka, H. Matsui, M. Ueda, and M. Daito, "A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40MS/s," IEEE J. Solid-State Circuits, vol.41, pp.883-890, Apr. 2006.
2. B. Murman and B. E. Boser, "A 12-bit 75-MS/s pipelined ADC using open-loop residue amplifier." IEEE J. Solid-State Circuits, vol.38, pp.2040-2050, Dec. 2003.
3. M. Furuta, S. Kawahito, and D. Miyazaki, "A Digital Calibration Technique for Capacitor Mismatch for Pipelined Analog-to-Digilal Converters," IEICE Trans. Electron., vol.E85-C, No.8, pp.1562-1568, Aug, 2002.