Analysis of PLL Clock Jitter in High-Speed Serial Links

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 50, Issue 11, 2003, Pages 879-886

  Hanumolu, Pavan Kumar ^a   Casper, Bryan ^b   Mooney, Randy ^b   Wei, Gu Yeon ^c   Moon, Un Ku ^a  

^a Oregon State University   (United States)

^b INTEL CORPORATION   (United States)

^c HARVARD UNIVERSITY   (United States)

Author keywords

Bit error rate (BER); Eye diagrams; Inter symbol interference; Jitter; Phase noise; Phase locked loops (PLL); Serial links

Indexed keywords

BIT ERROR RATE; CHANNEL CAPACITY; INTERSYMBOL INTERFERENCE; JITTER; PHASE LOCKED LOOPS; SIGNAL RECEIVERS; SPURIOUS SIGNAL NOISE; TRANSMITTERS;

HIGH-SPEED SERIAL LINKS; PHASE NOISES;

TELECOMMUNICATION LINKS;

EID: 0345293098     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSII.2003.819121     Document Type: Article

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