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Volumn , Issue , 2005, Pages 638-643

A unified optimization framework for equalization filter synthesis

Author keywords

Crosstalk; Equalizing filters; Linear programming; Optimal synthesis

Indexed keywords

LINEAR PROGRAMMING; MATRIX ALGEBRA; OPTIMIZATION; PROBLEM SOLVING;

EID: 27944453638     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dac.2005.193889     Document Type: Conference Paper
Times cited : (11)

References (15)
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    • Balamurugan, G.1    Shanbhag, N.2
  • 3
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    • Transmitter equalization for 4-GBPs signaling
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    • Dally, W.1    Poulton, J.2
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    • A 1.0625Gbps transceiver with 2x-oversampling and transmit signal pre-emphasis
    • A. Fiedler, R. Mactaggart, et al. A 1.0625Gbps transceiver with 2x-oversampling and transmit signal pre-emphasis. In Proc. of ISSCC97, pages 238-239, 1997.
    • (1997) Proc. of ISSCC97 , pp. 238-239
    • Fiedler, A.1    Mactaggart, R.2
  • 7
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    • Personal Communication
    • Ron Ho. Personal Communication, 2004
    • (2004)
    • Ho, R.1
  • 8
    • 4544247863 scopus 로고    scopus 로고
    • Design, modeling and characterization of high speed backplane interconnects
    • R. Kollipara, G.J. Yeh, et al. Design, Modeling and Characterization of High Speed Backplane Interconnects. High-Performance System Design Conf., 2003.
    • (2003) High-performance System Design Conf.
    • Kollipara, R.1    Yeh, G.J.2
  • 12
    • 0031146350 scopus 로고    scopus 로고
    • A 700-Mb/s/pin CMOS signaling interface using current integrating receivers
    • May
    • S. Sidiropoulos and M. Horowitz. A 700-Mb/s/pin CMOS signaling interface using current integrating receivers. IEEE J. Solid State Circuits, 32(5):681-690, May 1997.
    • (1997) IEEE J. Solid State Circuits , vol.32 , Issue.5 , pp. 681-690
    • Sidiropoulos, S.1    Horowitz, M.2
  • 13
    • 0042694574 scopus 로고    scopus 로고
    • Transmit pre-emphasis for high-speed time-division-multiplexed serial-link transceiver
    • V. Stojanovic, G. Ginis, and M. Horowitz. Transmit pre-emphasis for high-speed time-division-multiplexed serial-link transceiver. IEEE Trans. on Communications, 38:551-558, 2001.
    • (2001) IEEE Trans. on Communications , vol.38 , pp. 551-558
    • Stojanovic, V.1    Ginis, G.2    Horowitz, M.3
  • 14
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    • The Mathworks Inc. http://www.mathworks.com
  • 15
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    • Equalization and clock recovery for a 2.5-10 Gb/s 2-PAM/4-PAM backplane transceiver cell
    • Dec.
    • J.L. Zerbe, C.W. Werner, et al. Equalization and Clock Recovery for a 2.5-10 Gb/s 2-PAM/4-PAM Backplane Transceiver cell. IEEE J. Solid-State Circuits, 38(12):2121-2130, Dec. 2003.
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    • Zerbe, J.L.1    Werner, C.W.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.