Unified adaptivity optimization of clock and logic signals

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2007, Pages 125-130

  Hu, Shiyan ^a   Hu, Jiang ^a  

^a Department of Electrical and Computer Engineering   (United States)

Author keywords

Clock signal tuning; Logic signal tuning; Post silicon tuning; Robustness; Variation

Indexed keywords

ADAPTIVITY; AREA COST; BINARY SEARCH; CLOCK SIGNAL TUNING; CLOCK SIGNALLING; COMPUTER-AIDED DESIGN; DISCRETIZATION; FAST SIMULATION; INTERNATIONAL CONFERENCES; LATIN HYPERCUBE SAMPLING; LINEAR PROGRAMMING FORMULATIONS; LINEAR PROGRAMMING TECHNIQUES; LOGIC SIGNAL TUNING; LOGIC SIGNALS; PARAMETRIC YIELD; POST-SILICON TUNING; ROBUSTNESS; RUN-TIME; SOLUTION QUALITY; VARIATION; VLSI DESIGNS;

CLOCKS; COST REDUCTION; COSTS; DESIGN; DYNAMIC PROGRAMMING; ELECTRIC CLOCKS; FINANCE; INDUSTRIAL ECONOMICS; LINEARIZATION; MATHEMATICAL PROGRAMMING; NONMETALS; OPTIMIZATION; PARTICLE SIZE ANALYSIS; SILICON; SYSTEMS ENGINEERING; TUNING;

LINEAR PROGRAMMING;

EID: 50249136157     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2007.4397254     Document Type: Conference Paper

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