Utilizing shared data in chip multiprocessors with the Nahalal architecture

Annual ACM Symposium on Parallelism in Algorithms and Architectures

Volumn , Issue , 2008, Pages 1-10

  Guz, Zvika ^a   Keidar, Idit ^b   Kolodny, Avinoam ^b   Weiser, Uri C ^b  

^a Department of Electrical Engineering ^*

^b TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

Author keywords

Cache memories; Chip multiprocessors

Indexed keywords

CACHE ACCESS LATENCIES; CACHE COHERENCES; CACHE ORGANIZATIONS; CACHED DATUMS; CHIP MULTIPROCESSORS; IN CHIPS; PAPER ADDRESSES; PERFORMANCE GAINS; PRIVATE DATUMS; RUN TIMES; SHARED CACHES; SHARED DATUMS;

ARCHITECTURE; CACHE MEMORY; MULTIPROCESSING SYSTEMS; NANOTECHNOLOGY; SYSTEMS ANALYSIS;

COMPUTER ARCHITECTURE;

EID: 57349116176     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1378533.1378535     Document Type: Conference Paper

References (33)

1. R. Ho, K. Mai, and M. Horowitz, "The future of wires," Proceedings of IEEE,89(4), April 2001.
2. L. Hammond, B. A. Nayfeh, and K. Olukotun. "A Single-Chip Multiprocessor". IEEE Computer, September 1997
3. V. Agarwal, M. S. Hrishikesh, S.W. Keckler, and D. Burger. Clock rate vs. IPC: The end of the road for conventional microprocessors. ISCA-27, June 2000
4. WJ Dally and S. Lacy. VLSI Architecture: Past, Present, and Future, In Proceedings of the Advanced Research in VLSI conference, Jan. 1999, pp. 232-241.
5. C. Kim, D. Burger, and S. W. Keckler, "An adaptive, nonuniform cache structure for wire-delay dominated on-chip caches," In ASPLOS X, pages 211-222, Oct. 2002
6. S. Gochman, A. Mendelson, A. Naveh, A, and E. Rotem, "Introduction to Intel® Core™ Duo Processor Architecture," Intel Technology Journal, Volume 10, Issue 02. May 2006.
7. AMD white paper, "Key Architectural Features AMD Athlon™ 64 X2 Dual-Core and AMD Athlon™ X2 Dual-Core Processors," http://www.amd.com/gb-uk/Processors/ProductInformation/0"30-118-9485- 13041% 5E13043,00.html
8. AMD technical articles, "Barcelona's Innovative Architecture Is Driven by a New Shared Cache," http://developer.amd.com/article-print.jsp? id=173
9. W.A. Wulf and S.A. McKee, "Hitting the Memory Wall: Implications of the Obvious," Computer Architecture News, vol. 23, no. 1, pp. 14-24, Mar. 1995
10. B. M. Beckmann and D. A. Wood, "Managing wire delay in large chip multiprocessor caches," MICRO 37, Dec. 2004
11. J. Huh, C. Kim, H. Shafi, L. Zhang, D. Burger, and S.W. Keckler, "A substrate for Flexible CMP Cache Sharing," ICS 05, June, 2005
12. Z. Guz, I. Keidar, A. Kolodny, U. C. Weiser, "Nahalal: Cache Organization for Chip Multiprocessors", IEEE Computer Architecture Letters, vol. 6, no. 1, May 2007
13. B. M. Beckmann, M. R. Marty, and D. A. Wood, "ASR: Adaptive Selective Replication for CMP Caches," MICRO 39, December 2006
14. E. Howard, "Garden Cities of To-Morrow," London: Swan Sonnenschein & Co. Ltd, 1902
15. T. Y. Morad, U. C. Weiser, A. Kolodny, M. Valero, and E. Ayguadé, "Performance, Power Efficiency, and Scalability of Asymmetric Cluster Chip Multiprocessors," In Computer Architecture Letters, Volume 4, July 2005.
16. J. Chang and G. S. Sohi. "Cooperative Caching for Chip Multiprocessors," ISCA-33, June 2006
17. Z. Chishti, M. D. Powell, and T. N. Vijaykumar, "Optimizing Replication, Communication, and Capacity Allocation in CMPs," ISCA32, 2005.
18. J. Brown, R. Kumar, andD. Tullsen. "Proximity-Aware Directory-based Coherence for Multi-core Processor Architectures", 19th ACM Symposium on Parallelism in Algorithms and Architectures, SPAA, San Diego, June 2007
19. L. Jin and S. Cho, "Better than the Two: Exceeding Private and Shared Caches via Two-Dimensional Page Coloring", in Workshop on Chip Multiprocessor Memory Systems and Interconnects, 2007.
20. M. R. Marty and M. D. Hill, "Virtual Hierarchies to Support Server Consolidation", ISCA-34, June 2007.
21. C. Liu, A. Sivasubramaniam, M. Kandemir, and M. J. Irwin, "Enhancing L2 organization for CMPs with a center cell," IPDPS'06, April 2006.
22. L. Jin, and S. Cho, "Better than the two: Exceeding private and shared caches via two-dimensional page coloring," in Workshop on Chip Multiprocessor Memory Systems and Interconnects, 2007.
23. M. Zhang and K. Asanovic, "Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors" ISCA32, 2005.
24. P. S. Magnusson, M. Christensson, J. Eskilson, D. Forsgren, and G. Hallberg, "Simics: A full system simulation platform," IEEE Computer, 35(2):50-58, Feb. 2002.
25. R. Ricci, S. Barrus, D. Gebhardt, and R. Balasubramonian, "Leveraging Bloom Filters for Smart Search Within NUCA Caches", 7th Workshop on Complexity-Effective Design (WCED), June 2006.
26. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH-2 Programs: Characterization and Methodological Considerations. ISCA-22, June 1995.
27. V. Aslot, M. Domeika, R. Eigenmann, G. Gaertner, W. Jones, and B. Parady. SPEComp: A New Benchmark Suite for Measuring Parallel Computer Performance. In Workshop on OpenMP Applications and Tools, pages 1-10, July 2001.
28. P. Barford and M. Crovella. Generating representative web workloads for network and server performance evaluation. In Measurement and Modeling of Computer Systems, pages 151-160, June 1998.
29. http://www.zeus.com/products/zws/
30. http://www.spec.org/jbb2000/
31. V. J. Marathe, M. F. Spear, C. Heriot, A. Acharya, D. Eisenstat, W. N. Scherer III, and M. L. Scott, "Lowering the Overhead of Nonblocking Software Transactional Memory," TRANSACT 2006
32. R. Kumar, D. Tullsen, P. Ranganathan, N. Jouppi, and K. Farkas. "Single-ISA Heterogeneous Multi-core Architectures for Multithreaded Workload Performance." ISCA-31, June 2004.
33. C.K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V.J. Reddi, and K. Hazelwood, "Pin: Building Customized Program Analysis Tools with Dynamic Instrumentation," PLDI 2005.