A digital self-calibration algorithm for ADCs based on histogram test using low-linearity input signals

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 1378-1381

  Jin, Le ^a   Chen, Degang ^a   Geiger, Randall ^a  

^a Iowa State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODE-DENSITY; CORRECTION CODES; DIGITAL SELF-CALIBRATION; HIGH RESOLUTION; HIGH-SPEED HIGH-PRECISION; INPUT SIGNAL; MEMORY CELL; NON-LINEARITY; ON CHIPS; RAMP SIGNAL; SIMULATION RESULT;

CALIBRATION; LINEARIZATION; MULTICARRIER MODULATION;

ALGORITHMS;

EID: 37249009974     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464853     Document Type: Conference Paper

References (4)

1. International Technology Roadmap for Semiconductors, 2001 and 2003 edition, available online: http://public.itrs.net.
2. A. N. Karanicolas, H.-S. Lee, and K. L. Bacrania, "A 15-b 1- Msample/s Digitally Self-Calibrated Pipeline ADC," IEEE J. Solid- State Circuits, vol. 28, pp. 1207 - 1215, Dec. 1993.
3. O. E. Erdogan, P. J. Hurst, and S. H. Lewis, "A 12-b Digital- Background-Calibrated Algorithmic ADC with 90-dB THD," IEEE J. Solid-State Circuits, vol. 34, pp. 1812 - 1820, Dec. 1999
4. L. Jin, K. Parthasarathy, T. Kuyel, D. Chen and R. L. Geiger, "Linearity Testing of Precision Analog-to-Digital Converters Using Stationary Nonlinear Inputs," in Proc. 2003 International Test Conference, pp. 218 - 227, Charlotte, NC, Oct 2003.