True background calibration technique for pipelined ADC

Electronics Letters

Volumn 36, Issue 9, 2000, Pages 786-788

  Sonkusale, S ^a   Van Der Spiegel, J ^a   Nagaraj, K ^b  

^a UNIVERSITY OF PENNSYLVANIA   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CALIBRATION; CAPACITORS; COMPUTER SIMULATION; ERROR CORRECTION; OPERATIONAL AMPLIFIERS;

DIGITAL BACKGROUND CALIBRATION TECHNIQUE; LEAST MEAN SQUARES ALGORITHM; PIPELINED ANALOGUE TO DIGITAL CONVERTER;

ANALOG TO DIGITAL CONVERSION;

EID: 0033743496     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20000610     Document Type: Article

References (5)

1. LEE, HAE-SEUNG: 'A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic adc', IEEE J. Solid-State Circuits, 1994, SC-29, (4), pp. 509-515
2. MOON, UN-KU, and SONG, BANG-SUP: 'Background digital calibration techniques for pipelined adc's', IEEE Trans., 1997, CASII-44, (2), pp. 102-109
3. INGINO, J., and WOOLEY, B.: 'A continuously calibrated 12-b, 10-ms/ s, 3.3-v a/d converter', IEEE J. Solid-State Circuits, 1998, SC-33, (12), pp. 1920-1931
4. LEWIS, S.H., FETTERMAN, H.S., GROSS, G.F., RAMACHANDRAN, R., and VISWANATHAN, T.R.: 'A 10-b 20-msample/s analog-to-digital converter', IEEE J. Solid-State Circuits, 1992, SC-27, (3), pp. 351-358
5. NAGARAJ, K.: 'Area-efficient self-calibration technique for pipelined algorithmic a/d converters', IEEE Trans., 1996, CASII-43, (7), pp. 540-544