A cost-effective histogram test-based algorithm for digital calibration of high-precision pipelined ADCs

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 4831-4834

  Dai, Xin ^a   Chen, Degang ^a   Geiger, Randall ^a  

^a Iowa State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CALIBRATION ALGORITHM; CODE DENSITY; CORRECTION CODES; DIGITAL CALIBRATIONS; HIGH-PRECISION; HIGH-SPEED HIGH-PRECISION; LINEARITY ERRORS; MEMORY CELL; ON CHIPS; PIPELINED ADCS; SELF CALIBRATION; SELF-CALIBRATION ALGORITHMS; SIMULATION RESULT;

CALIBRATION; CARRY LOGIC; ERROR COMPENSATION; LINEARIZATION; LOGIC CIRCUITS; MULTICARRIER MODULATION; PIPELINE CODES; SWITCHING CIRCUITS;

ALGORITHMS;

EID: 51549106235     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465714     Document Type: Conference Paper

References (4)

1. B.-S. Song, M. F. Tompset, and K.R. Lakshmikumar, "A 12-b 1Msample/s capacitor error-averaging pipelined A/D converter," IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1324-1333, Dec. 1988.
2. H. Ohara et al., "A CMOS programmable self-calibrating 13-b eightchannel data acquisition peripheral," IEEE J. Solid-State Circuits, vol. SC-22, pp. 930-938, Dec. 1987.
3. E. G. Soenen and R. L. Geiger, "An architecture and an algorithm for fully digital correction of monolithic pipelined ADCs," IEEE Trans. Circuits Syst. II, vol. 42, pp. 143-153, Mar. 1995.
4. A. N. Karanicolas, H.-S. Lee, and K. L. Bacrania, "A 15-b 1- Msample/s digitally self-calibrated pipeline ADC," IEEE J. Solid- State Circuits, vol. 28, pp. 1207-1215, Dec. 1993