Stress-induced hump effects of p-channel polycrystalline silicon thin-film transistors

IEEE Electron Device Letters

Volumn 29, Issue 12, 2008, Pages 1332-1335

  Huang, Ching Fang ^a   Peng, Cheng Yi ^a   Yang, Ying Jhe ^a   Sun, Hung Chang ^a   Chang, Hung Chih ^a   Kuo, Ping Sheng ^a   Chang, Huan Lin ^a   Liu, Chee Zxaing ^a   Liu, Chee Wee ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Hump; Poly Si; Positive bias temperature instability (PBTI); Thin film transistor (TFT)

Indexed keywords

ELECTRIC FIELDS; ELECTRIC INSULATORS; ELECTRON TUBE DIODES; POLYSILICON; SEMICONDUCTING ORGANIC COMPOUNDS; SEMICONDUCTING SILICON; SEMICONDUCTING SILICON COMPOUNDS; SILICON; THIN FILM DEVICES; THIN FILM TRANSISTORS; TRANSISTORS;

CHANNEL TRANSISTORS; CHANNEL WIDTHS; ELECTRIC FLUX DENSITIES; ELECTRON TRAPPING; GATE INSULATORS; HIGH TEMPERATURES; HUMP; HUMP EFFECTS; POLY-SI; POLYCRYSTALLINE SILICONS; POSITIVE BIAS TEMPERATURE INSTABILITIES; POSITIVE BIAS TEMPERATURE INSTABILITY (PBTI); POSITIVE VOLTAGES; SUBTHRESHOLD REGIONS; THIN-FILM TRANSISTOR (TFT); TRAPPED ELECTRONS;

TURBULENT FLOW;

EID: 57049096959     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2008.2007306     Document Type: Article

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