메뉴 건너뛰기




Volumn 26, Issue 1, 2005, Pages 23-25

A new low-power pMOS poly-Si inverter for AMDs

Author keywords

Active matrix display (AMD); Boot strapping; Driving circuit; pMOS inverter; Poly Si thin film transistor (TFT)

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC INVERTERS; LIGHT EMITTING DIODES; LIQUID CRYSTAL DISPLAYS; POLYSILICON; POWER ELECTRONICS; SEMICONDUCTOR DEVICE MANUFACTURE; THIN FILM TRANSISTORS;

EID: 12444285868     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2004.839217     Document Type: Article
Times cited : (19)

References (7)
  • 1
    • 1642414270 scopus 로고    scopus 로고
    • "P-type technology for large size low temperature poly-Si TFT-LCDs"
    • Y. M. Ha, "P-type technology for large size low temperature poly-Si TFT-LCDs," in SID Tech. Dig., 2000, pp. 1116-1119.
    • (2000) SID Tech. Dig. , pp. 1116-1119
    • Ha, Y.M.1
  • 2
    • 0032050442 scopus 로고    scopus 로고
    • "Analysis of drain field and hot carrier stability of poly-Si thin film transistors"
    • J.R. Ayres, D. Brotherton, D. J. McCulloch, and M. J. Trainor, "Analysis of drain field and hot carrier stability of poly-Si thin film transistors," Jpn. J. Appl. Phys., vol. 37, pp. 1801-1808, 1998.
    • (1998) Jpn. J. Appl. Phys. , vol.37 , pp. 1801-1808
    • Ayres, J.R.1    Brotherton, D.2    McCulloch, D.J.3    Trainor, M.J.4
  • 3
    • 0035471242 scopus 로고    scopus 로고
    • "Reliability of low temperature poly-Silicon TFTs under inverter operation"
    • Oct
    • Y. Uraoka, T. Hatayama, T. Fuyuki, T. Kawamura, and Y. Tsuchihashi, "Reliability of low temperature poly-Silicon TFTs under inverter operation," IEEE Trans. Electron Devices, vol. 48, no. 10, pp. 2370-2374, Oct. 2001.
    • (2001) IEEE Trans. Electron Devices , vol.48 , Issue.10 , pp. 2370-2374
    • Uraoka, Y.1    Hatayama, T.2    Fuyuki, T.3    Kawamura, T.4    Tsuchihashi, Y.5
  • 4
    • 0017983253 scopus 로고
    • "Design considerations in single-channel MOS analog integrated circuits - A tutorial"
    • Mar
    • Y. P. Tsividis, "Design considerations in single-channel MOS analog integrated circuits - a tutorial," IEEE J. Solid-State Circuit, vol. 13, no. 3, pp. 383-391, Mar. 1978.
    • (1978) IEEE J. Solid-State Circuit , vol.13 , Issue.3 , pp. 383-391
    • Tsividis, Y.P.1
  • 7
    • 0015347228 scopus 로고
    • "Eliminating threshold losses in MOS circuits by bootstrapping using varactor coupling"
    • Mar
    • R. E. Joynson, J. L. Mundy, J. F. Burgess, and C. Neugebauer, "Eliminating threshold losses in MOS circuits by bootstrapping using varactor coupling," IEEE J. Solid-State Circuits, vol. SC-7, no. 3, pp. 217-224. Mar. 1972.
    • (1972) IEEE J. Solid-State Circuits , vol.SC-7 , Issue.3 , pp. 217-224
    • Joynson, R.E.1    Mundy, J.L.2    Burgess, J.F.3    Neugebauer, C.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.