Novel corner rounding process for shallow trench isolation utilizing MSTS (Micro-Structure Transformation of Silicon)

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1998, Pages 137-140

  Matsuda, S ^a   Sato, T ^a   Yoshimura, H ^a   Takegawa, Y ^a   Sudo, A ^a   Mizushima, I ^a   Tsunashima, Y ^a   Toyoshima, Y ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; MOSFET DEVICES; SEMICONDUCTOR DEVICE STRUCTURES; SILICON WAFERS;

PARASITIC CORNER TRANSISTORS; REVERSE NARROW CHANNEL EFFECT; SHALLOW TRENCH ISOLATION (STI);

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0032271790     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)