The nanoscale silicon accumulation-mode MOSFET - A comprehensive numerical study

IEEE Transactions on Electron Devices

Volumn 55, Issue 11, 2008, Pages 2946-2959

  Iqbal, Md Mash Hud ^a   Hong, Yi ^a   Garg, Pranav ^a   Udrea, Florin ^a   Migliorato, Piero ^a   Fonash, Stephen J ^b  

^a UNIVERSITY OF CAMBRIDGE   (United Kingdom)

^b PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

Accumulation field effect transistor (FET); Nanoribbon (NR) FET; Nanoscale thickness thin film transistors (TFTs); Nanowire (NW) FET; Simple processing FET

Indexed keywords

ELECTRIC WIRE; LEAKAGE CURRENTS; MESFET DEVICES; MOS DEVICES; MOSFET DEVICES; NANOSTRUCTURED MATERIALS; NANOSTRUCTURES; NANOTECHNOLOGY; NANOWIRES; NUMERICAL ANALYSIS; SEMICONDUCTING INDIUM; SEMICONDUCTING SILICON COMPOUNDS; SILICON; THIN FILM DEVICES; THIN FILM TRANSISTORS; TRANSISTORS;

ACCUMULATION FIELD-EFFECT TRANSISTOR (FET); CURRENT PATHS; FILM MATERIALS; GATE CAPACITANCES; GATE LENGTHS; MATERIAL PARAMETERS; MOS FETS; NANORIBBON (NR) FET; NANORIBBONS; NANOSCALE; NANOSCALE DIMENSIONS; NANOSCALE-THICKNESS THIN-FILM TRANSISTORS (TFTS); NUMERICAL SIMULATIONS; NUMERICAL STUDIES; SEMI-CONDUCTORS; SILICON NANOWIRES; SIMPLE-PROCESSING FET; SOURCE AND DRAINS; STATE CURRENTS; SUBTHRESHOLD SWINGS; TRANSISTOR OPERATIONS; TRANSISTOR STRUCTURES;

FIELD EFFECT TRANSISTORS;

EID: 56549119302     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2008.2005174     Document Type: Article

References (24)

1. X. Duan, Y. Huang, and C. M. Lieber, "Nonvolatile memory and programmable logic from molecule-gated nanowires," Nano Lett., vol. 2, no. 5, pp. 487-490, May 2002.
2. M. C. McAlpine, R. S. Friedman, S. Jin, K. Lin, W. U. Wang, and C. M. Lieber, "High-performance nanowire electronics and photonics on glass and plastic substrates," Nano Lett., vol. 3, no. 11, pp. 1531-1535, Nov. 2003.
3. X. Duan, C. Niu, V. Sahi, J. Chen, J. Wallace Parce, S. Empedocles, and J. L. Goldman, "High-performance thin-film transistors using senticonductor nanowires and nanoribbons," Nature, vol. 425, no. 6855, pp. 274-278, Sep. 2003.
4. F. L. Yang et al., "5 nm-gate nanowire FinFET," in VLSI Symp. Tech. Dig., 2004, pp. 196-197.
5. Y. Cui, Q. Wei, H. Park, and C. M. Lieber, "Nanowire nanosensors for highly sensitive and selective detection of biological and chemical species," Science, vol. 293, no. 5533, pp. 1289-1292, Aug. 2001.
6. Z. Li, Y Chen, X. Li, T. I. Kamins, K. Nauka, and R. S. Williams, "Sequence-specific label-free DNA sensors based on silicon nanowires," Nano Lett., vol. 4, no. 2, pp. 245-247, Feb. 2004.
7. K. Byon, D. Tham, J. E. Fischer, and A. T. Johnson, "Synthesis and postgrowth doping of silicon nanowires," Appl. Phys. Lett., vol. 87, no. 19, p. 193 104, Nov. 2005.
8. J. Xiang, W. Lu, Y Hu, Y. Wu, H. Yan, and C. M. Lieber, "Ge/Si nanowire heterostructures as high-performance field-effect transistors," Nature, vol. 441, no. 7092, pp. 489-493, May 2006.
9. N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H. Tung, R. Kumar, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong, "High-performance fully depleted silicon nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices," IEEE Electron Device Lett., vol. 27, no. 5, pp. 383-386, May 2006.
10. G. Liang, J. Xiang, N. Kharche, G. Klimeck, C. M. Lieber, and M. Lundstrom, "Performance analysis of a Ge/Si core/shell nanowire field-effect transistor," Nano Lett., vol. 7, no. 3, pp. 642-646, Mar. 2007.
11. Y. Shan, S. Ashok, and S. J. Fonash, "Unipolar accumulation-type transistor configuration implemented using Si nanowires," Appl. Phys. Lett., vol. 91, no. 9, p. 093 518, Aug. 2007.
12. Y. Shan and S. J. Fonash, "Self-assembling silicon nanowires for device applications using the nanochannel-guided 'Growth-in-Place' approach," ACS Nano, vol. 2, no. 3, pp. 429-434, 2008.
13. S. J. Fonash, M. M. Iqbal, F. Udrea, and P. Mighorato, "Numerical modeling study of the unipolar accumulation transistor," Appl. Phys. Lett., vol. 91, no. 19, p. 193 508, Nov. 2007.
14. TCAD-Sentaurus User Manual, Synopsys, Inc., Mountain View, CA, 2005. Version X-2005, 10.
15. S. Sze, Physics of Semiconductor Devices. New York: Wiley-Interscience, 1981.
16. C. Lombardi, S. Manzini, A. Saporito, and M. Vanzi, "A physically based mobility model for numerical simulation of nonplanar devices," IEEE Trans. Comput. -Aided Design Integr. Circuits Syst., vol. 7, no. 11, pp. 1164-1171, Nov. 1988.
17. G. Masetti, M. Severi, and S. Solmi, "Modeling of carrier mobility against carrier concentration in arsenic-, phosphorus-, and boron-doped silicon," IEEE Trans. Electron Devices, vol. ED-30, no. 7, pp. 764-769, Jul. 1983.
18. C. Canali, G. Majni, R. Mmder, and G. Ottaviani, "Electron and hole drift velocity measurements in silicon and their empirical relation to electric field and temperature," IEEE Trans. Electron Devices, vol. ED-22, no. 11, pp. 1045-1047, Nov. 1975.
19. R. Chan, S. Datta, M. Doczy, B. Doyle, J. Kavalieros, and M. Metz, "High-k/metal-gate stack and its MOSFET characteristics," IEEE Electron Device Lett., vol. 25, no. 6, pp. 408-410, Jun. 2004.
20. S. Pidin, T. Mori, R. Nakamura, T. Saiki, R. Tanabe, S. Satoh, M. Kase, K. Hashmoto, and T. Sugh, "MOSFET current drive optimization using silicon nitride capping layer for 65-nm technology node," in VLSI Symp. Tech. Dig., 2004, pp. 54-55.
21. D. Striakhilev, A. Nathan, Y Vygranenko, and A. Czang-Ho Lee, "Amorphous silicon display backplanes on plastic substrates," J. Display Technol., vol. 2, no. 4, pp. 364-371, Dec. 2006.
22. K. Long, A. Z. Kattamis, I.-C. Cheng, H. Gleskova, S. Wagner, and J. C. Sturm, "Stability of amorphous-silicon TFTs deposited on clear plastic substrates at 250 °C to 280 °C," IEEE Electron Device Lett., vol. 27, no. 2, pp. 111-113, Feb. 2006.
23. Y. Lee, S. Bae, and S. J. Fonash, "High-performance nonhydrogenated nickel-Induced laterally crystallized p-channel poly-Si TFTs," IEEE Electron Device Lett., vol. 26, no. 12, pp. 900-902, Dec. 2005.
24. J. Jang, "TFT technologies for large area electronics," ECS Trans. vol. 8, no. 2, pp. 39-43, 2007.