MOSFET current drive optimization using silicon nitride capping layer for 65-nm technology node

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2004, Pages 54-55

  Pidin, S ^a   Mori, T ^a   Nakamura, R ^a   Saiki, T ^a   Tanabe, R ^a   Satoh, S ^a   Kase, M ^a   Hashimoto, K ^a   Sugii, T ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CARRIER MOBILITY; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; OPTIMIZATION; PARAMETER ESTIMATION; RAPID THERMAL ANNEALING; SILICON NITRIDE;

CAPPING LAYERS; CURRENT DRIVES; LAYER THICKNESS; TENSILE STRAINS;

MOSFET DEVICES;

EID: 4544268942     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/vlsit.2004.1345389     Document Type: Conference Paper

References (5)

1. T.Ghani et al., IEDM Tech. Dig., pp.978-980, 2003.
2. S.Thompson et al., IEDM Tech. Dig., pp.61-64, 2002.
3. V.Chan et al., IEDM Tech. Dig., pp.77-80, 2003.
4. Y.Kumagai et al., SSDM, p.14-15, 2002.
5. K.Rim et al., IEDM Tech. Dig., pp.43-46, 2002.