Impact of asymmetric channel configuration on the linearity of double-gate SOI MOSFETs

Proceedings of the Sixth International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2006 - Final Program and Technical Digest

Volumn , Issue , 2006, Pages 187-194

  Pavanello, Marcelo Antonio ^a,b   Cerdeira, Antonio ^c   Martino, João Antonio ^a,b   Raskin, Jean Pierre ^d   Flandre, Denis ^d  

^a CENTRO UNIVERSITÁRIO DA FEI   (Brazil)

^b UNIVERSITY OF SÃO PAULO   (Brazil)

^c DEPARTAMENTO DE FÍSICA   (Mexico)

^d UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

Double gate; Harmonic distortion; Linearity; MOSFET

Indexed keywords

DOUBLE GATE; GATE ALL AROUND ARCHITECTURE; GRADED CHANNELS (GC); SINUSOIDAL SIGNALS;

BIAS VOLTAGE; CHANNEL ESTIMATION; GATES (TRANSISTOR); HARMONIC DISTORTION; POWER AMPLIFIERS; SILICON ON INSULATOR TECHNOLOGY;

MOSFET DEVICES;

EID: 34250757086     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCDCS.2006.250859     Document Type: Conference Paper

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