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Volumn 37, Issue 1, 2006, Pages 31-37

Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS

Author keywords

Analog circuits; Graded channel SOI nMOSFET; Operational transconductance amplifier; OTA; Silicon on insulator technology

Indexed keywords

BANDWIDTH; COMPUTER SIMULATION; MOSFET DEVICES; SILICON ON INSULATOR TECHNOLOGY; TRANSCONDUCTANCE;

EID: 28044432778     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2005.06.010     Document Type: Article
Times cited : (16)

References (19)
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    • Chuang, C.T.1    Lu, P.F.2    Anderson, C.J.3
  • 4
    • 0030081408 scopus 로고    scopus 로고
    • Improvement of SOI MOS current-mirror performances using serial-parallel association of transistors
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    • De Ceuster, D.1    Flandre, D.2    Colinge, J.P.3    Cristoloveanu, S.4
  • 5
    • 0029520355 scopus 로고
    • A high performance 0.1 μm MOSFET with asymmetric channel profile
    • A. Hiroki, S. Odanaka, and A. Hori A high performance 0.1 μm MOSFET with asymmetric channel profile IEDM Technical Digest 1995 p. 439
    • (1995) IEDM Technical Digest
    • Hiroki, A.1    Odanaka, S.2    Hori, A.3
  • 6
    • 84908155589 scopus 로고    scopus 로고
    • Realization on 0.1 μm asymmetric channel MOSFET with excellent short-channel performance and reliability
    • B. Cheng, V. Ramgopal Rao, B. Ikegami, and J.C.S. Woo Realization on 0.1 μm asymmetric channel MOSFET with excellent short-channel performance and reliability Proceedings of ESSDERC 98 1998 p. 520
    • (1998) Proceedings of ESSDERC 98
    • Cheng, B.1    Ramgopal Rao, V.2    Ikegami, B.3    Woo, J.C.S.4
  • 9
    • 0033751937 scopus 로고    scopus 로고
    • Analog performance and application of graded-channel fully depleted SOI MOSFETs
    • M.A. Pavanello, J.A. Martino, V. Dessard, and D. Flandre Analog performance and application of graded-channel fully depleted SOI MOSFETs Solid-State Electronics 44 2000 1219 1222
    • (2000) Solid-State Electronics , vol.44 , pp. 1219-1222
    • Pavanello, M.A.1    Martino, J.A.2    Dessard, V.3    Flandre, D.4
  • 10
    • 0033639792 scopus 로고    scopus 로고
    • An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics
    • M.A. Pavanello, J.A. Martino, V. Dessard, and D. Flandre An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics Electrochemistry Solid-State Letters 3 1 2000 50 52
    • (2000) Electrochemistry Solid-State Letters , vol.3 , Issue.1 , pp. 50-52
    • Pavanello, M.A.1    Martino, J.A.2    Dessard, V.3    Flandre, D.4
  • 14
    • 0036680370 scopus 로고    scopus 로고
    • Analog circuit design using graded-channel silicon-on-insulator nMOSFETs
    • M.A. Pavanello, J.A. Martino, and D. Flandre Analog circuit design using graded-channel silicon-on-insulator nMOSFETs Solid-State Electronics 46 8 2002 1215 1225
    • (2002) Solid-State Electronics , vol.46 , Issue.8 , pp. 1215-1225
    • Pavanello, M.A.1    Martino, J.A.2    Flandre, D.3
  • 15
    • 0030241117 scopus 로고    scopus 로고
    • A gm/ID Based Methodology for the Design of CMOS Analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA
    • F. Silveira, D. Flandre, and P.G.A. Jespers A gm/ID Based Methodology for the Design of CMOS Analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA IEEE Journal of Solid-State Circuits 31 9 1996
    • (1996) IEEE Journal of Solid-State Circuits , vol.31 , Issue.9
    • Silveira, F.1    Flandre, D.2    Jespers, P.G.A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.