메뉴 건너뛰기




Volumn , Issue , 2008, Pages 203-208

A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; APPLICATIONS; EMBEDDED SYSTEMS; MOTION ESTIMATION;

EID: 54949142209     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2008.4629932     Document Type: Conference Paper
Times cited : (27)

References (19)
  • 1
    • 0141717701 scopus 로고    scopus 로고
    • Closing the SoC Design Gap
    • J. Henkel, "Closing the SoC Design Gap", IEEE Computer, vol. 36, issue 9, pp. 119-121, 2003.
    • (2003) IEEE Computer , vol.36 , Issue.9 , pp. 119-121
    • Henkel, J.1
  • 6
    • 51549087415 scopus 로고    scopus 로고
    • Run-time Instruction Set Selection in a Transmutable Embedded Processor
    • DAC, pp
    • L. Bauer, M. Shafique, J. Henkel, "Run-time Instruction Set Selection in a Transmutable Embedded Processor", Design Automation Conference (DAC), pp. 56-61, 2008.
    • (2008) Design Automation Conference , pp. 56-61
    • Bauer, L.1    Shafique, M.2    Henkel, J.3
  • 7
    • 0028768023 scopus 로고
    • A High-Performance Mieroarchi-tecture with Hardware-Programmable Functional Units
    • R. Razdan, M. D. Smith, "A High-Performance Mieroarchi-tecture with Hardware-Programmable Functional Units", Intl. Symposium on Microarchitecture, pp. 172-180, 1994.
    • (1994) Intl. Symposium on Microarchitecture , pp. 172-180
    • Razdan, R.1    Smith, M.D.2
  • 9
    • 0032627649 scopus 로고    scopus 로고
    • Memory interfacing and instruction specification for reconfigurable processors
    • J. Jacob, P. Chow, "Memory interfacing and instruction specification for reconfigurable processors", Int'l Symposium on FPGAs, pp. 145-154, 1999.
    • (1999) Int'l Symposium on FPGAs , pp. 145-154
    • Jacob, J.1    Chow, P.2
  • 10
    • 0033703884 scopus 로고    scopus 로고
    • CHIMAERA: A High Performance Architecture with a tightly coupled reconfigurable functional unit
    • ISCA, pp
    • Z. A. Ye et al, "CHIMAERA: a High Performance Architecture with a tightly coupled reconfigurable functional unit", Intl. Symp. on Computer Architecture (ISCA), pp. 225-235, 2000.
    • (2000) Intl. Symp. on Computer Architecture , pp. 225-235
    • Ye, Z.A.1
  • 11
    • 8744241430 scopus 로고    scopus 로고
    • S. Vassiliadis, et al., The MOLEN polymorphic processor, Trans, on Computers, 53, issue 11, pp. 1363-1375, 2004.
    • S. Vassiliadis, et al., "The MOLEN polymorphic processor", Trans, on Computers, vol. 53, issue 11, pp. 1363-1375, 2004.
  • 12
    • 51549116195 scopus 로고    scopus 로고
    • Managing a Reconfigurable Processor in a General Purpose Workstation Environment
    • M. Dales, "Managing a Reconfigurable Processor in a General Purpose Workstation Environment", Design Automation and Test in Europe (DATE), pp. 980-985, 2003.
    • (2003) Design Automation and Test in Europe (DATE) , pp. 980-985
    • Dales, M.1
  • 13
    • 33748420512 scopus 로고    scopus 로고
    • R. Lysecky, G Stitt, F. Vahid, Warp Processors, Transaction on Design Automation of Electronic Systems (TODAES), 11, issue 3, pp. 659-681, 2006.
    • R. Lysecky, G Stitt, F. Vahid, "Warp Processors", Transaction on Design Automation of Electronic Systems (TODAES), vol. 11, issue 3, pp. 659-681, 2006.
  • 14
    • 0036382691 scopus 로고    scopus 로고
    • Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and de-fragmentation
    • Z. Li, S. Hauck, "Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and de-fragmentation", Int'l Symp. on FPGAs, pp. 187-195, 2002.
    • (2002) Int'l Symp. on FPGAs , pp. 187-195
    • Li, Z.1    Hauck, S.2
  • 15
    • 34247607804 scopus 로고    scopus 로고
    • The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-Based Computer
    • M. Majer, J. Teich, A. Ahmadinia, C. Bobda, "The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-Based Computer", VLSI Signal Processing Systems, pp. 15-31, 2007.
    • (2007) VLSI Signal Processing Systems , pp. 15-31
    • Majer, M.1    Teich, J.2    Ahmadinia, A.3    Bobda, C.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.