RISPP: Rotating instruction set processing platform

Proceedings - Design Automation Conference

Volumn , Issue , 2007, Pages 791-796

  Bauer, Lars ^a   Shafique, Muhammad ^a   Kramer, Simon ^a   Henkel, Jörg ^a  

^a UNIVERSITY OF KARLSRUHE   (Germany)

Author keywords

ASIP; Extensible embedded processors; Reconfigurable computing; Run time adaptation

Indexed keywords

ADAPTIVE CONTROL SYSTEMS; COMPUTER HARDWARE; ENERGY EFFICIENCY; IMAGE CODING; LOGIC DESIGN; PROGRAM PROCESSORS; RESPONSE TIME (COMPUTER SYSTEMS);

ASIP; RECONFIGURABLE COMPUTING; RISPP; RUN-TIME ADAPTATION;

EMBEDDED SYSTEMS;

EID: 34547249230     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2007.375272     Document Type: Conference Paper

References (31)

1. Arctangent processor. ARC Int'l (www.are.eom/eonfigurableeores/)
2. CoWare Ine, LISATek (www.eoware.eom/)
3. LISA (http://servus.ert.rwth-aaehen.de/lisa/)
4. Target Compiler (http://www.retarget.eom/)
5. SP-5Flex DSP Core, 3DSP (www.3dsp.eom/sp5_flex.shtml)
6. Stretch processor (www.stretehinc.eom)
7. Xilinx Corp. "XAPP 290: Two Flows for Partial Reconfiguration: Module Based or Difference Based", (www.xilinx.eom)
8. Xtensa processor, Tensiliea Inc. (www.tensiliea.com)
9. ITU-T Reo. H.264 and ISO/IEC 14496-10:2005 (E) (MPEG-4 AVC) "Advanced video coding for generic audiovisual services", 2005
10. J Ostermann, et al "Video coding with H.264/AVC: tools, performance, and complexity", IEEE Circuits and Systems, 2004
11. S Kobayashi, H Mita, Y Takeuehi, M Imai: "Design space exploration for dsp applications using the ASIP development system PEAS-III", ICASSP 2002
12. A Hoffmann et al. "A novel methodology for the design of application-specific instruction-set processors (ASIPs) using a machine description language", IEEE Trans. on CAD of Int. Circ. and Syst. 01
13. A Halambi et al. "Expression: A language for architecture exploration through compiler/simulator retargetability", DATE, 1999
14. J Henkel "Closing the SoC Design Gap", IEEE Computer Volume 36, Issue 9, September 2003
15. K Keutzer, S Malik, AR Newton "From ASIC to ASIP: the next design discontinuity", IEEE Int'l Conf. on Computer Design, 2002
16. N Cheung, J Henkel, S Parameswaran "Rapid configuration & instruction selection for an ASIP: a case study", DATE, 2003
17. K Atasu, L Pozzi, P Ienne "Automatic application-specific instruction-set extensions under microarchitectural constraints", DAC, 2003
18. F Sun, S Ravi, A Raghunathan, NK Jha "A scalable application-specific processor synthesis methodology", ICCAD, 2003
19. N Cheung, S Parameswaran, J Henkel "A quantitative study and estimation models for extensible instructions in embedded processors", ICCAD, 2004
20. G Braun, et al. "A novel approach for flexible and consistent ADL-driven ASIP design"[Pl], DAC, 2004
21. P Biswas, et al. "Introduction of local memory elements in instruction set extensions", DAC, 2004
22. R Hartenstein "A decade of reconfigurable computing: a visionary retrospective", DATE, 2001
23. K Compton, S Hauck "Reconfigurable computing: a survey of systems and software", ACM Computing Surveys 2002
24. F Barat, R Lauwereins "Reconfigurable instruction set processors: a survey", RSP 2000
25. S Vassiliadis, et al. "The MOLEN polymorphic processor", IEEE Transaction on Computers, 2004
26. RD Wittig, P Chow "OneChip: an FPGA processor with reeonfigurable logic", IEEE Symp. FCCM, 1996
27. JE Carrillo, P Chow "The effect of reconfigurable units in superscalar processors", Int'l Symp. on FPGAs, 2001
28. T Cormen, C Leiserson, R Rivest "Introduction to Algorithms", MIT Press, 23rd printing, 1999, ISBN 0-262-03141-8
29. Z Li, S Hauek: "Configuration prefetching techniques for partial reconfigurable coprocessors with relocation and defragmentation", Int'l Symp. on FPGAs, 2002
30. L Bauer, M Shafique, D Teufel, J Henkel: "A Self-Adaptive Extensible Embedded Processor", SASO 2007 (accepted for publication)
31. P Brisk, A Kaplan, M Sarrafzadeh "Area-efficient instruction set synthesis for reconfigurable system-on-chip designs", DAC 2004