Effect of NBTI degradation on transistor variability in advanced technologies

IEEE International Integrated Reliability Workshop Final Report

Volumn , Issue , 2007, Pages 18-21

  Pae, S ^a   Maiz, J ^a   Prasad, C ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GATES (TRANSISTOR);

ADVANCED TECHNOLOGY; DEVICE AGING; GATE OXIDE; OXIDE AREA; PRODUCT PERFORMANCE; SCALINGS;

NEGATIVE BIAS TEMPERATURE INSTABILITY;

EID: 49549100226     PISSN: 19308841     EISSN: 23748036     Source Type: Conference Proceeding    
DOI: 10.1109/IRWS.2007.4469214     Document Type: Conference Paper

References (10)

1. M. Agostinelli et al., IEDM, pp. 174-177, 2005.
2. A. Krishnan et al., IEDM, 2006.
3. D. Burnett et al., VLSI, pp. 15-16, 1993.
4. P. Moens et al., IRPS, pp. 214-221, 2003.
5. K. Mueller et al., IRPS, pp.426-429, 2004.
6. J. Maiz, IRW, Invited talk, 2006.
7. S. Rauch, TDMR, pp. 89-93, 2002.
8. M. Agostinelli et al., IRPS, pp. 529-532, 2005.
9. R. Keyes, IEEE JSSC, pp. 245-247, 1975.
10. J. Pineda de Gyvez et al., VTS, pp. 145-150, 2003.