Threshold voltage mismatch (ΔVT) fault modeling

Proceedings of the IEEE VLSI Test Symposium

Volumn 2003-January, Issue , 2003, Pages 145-150

  Pineda De Gyvez, J ^a   Rodriguez Montanes R ^a,b  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

Circuit faults; Circuit simulation; Circuit synthesis; Clocks; CMOS technology; Delay; Fluctuations; Leakage current; Semiconductor device manufacture; Threshold voltage

Indexed keywords

CIRCUIT SIMULATION; CLOCKS; CMOS INTEGRATED CIRCUITS; DESIGN; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; LEAKAGE CURRENTS; LOW POWER ELECTRONICS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICES; VLSI CIRCUITS;

CIRCUIT FAULTS; CIRCUIT SYNTHESIS; CMOS TECHNOLOGY; DELAY; FLUCTUATIONS;

THRESHOLD VOLTAGE;

EID: 54949126668     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.2003.1197645     Document Type: Conference Paper

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