Probabilistic approach for yield analysis of dynamic logic circuits

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 55, Issue 8, 2008, Pages 2238-2248

  Brusamarello, Lucas ^a   da Silva, Roberta ^a   Wirth, Gilson I ^a   Reis, Ricardo A L ^a  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

Design for yield; Monte Carlo methods; Probabilistic analysis; Process variability; VLSI; Yield estimation

Indexed keywords

COMPUTATION THEORY; COMPUTATIONAL EFFICIENCY; ERRORS; GATES (TRANSISTOR); LEAKAGE CURRENTS; LOGIC CIRCUITS; LOGIC GATES; MONTE CARLO METHODS; NUMERICAL METHODS; THRESHOLD VOLTAGE; TIMING CIRCUITS;

DESIGN FOR YIELDS; PROBABILISTIC ANALYSIS; PROCESS VARIABILITY; VLSI; YIELD ESTIMATION;

COMPUTER CIRCUITS;

EID: 54749148371     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.918141     Document Type: Article

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