Variable threshold voltage keeper for contention reduction in dynamic circuits

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn 2002-January, Issue , 2002, Pages 314-318

  Kursun, Volkan ^a   Friedman, Eby G ^a  

^a University of Rochester   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; THRESHOLD VOLTAGE;

CARRY LOOK-AHEAD ADDER; CIRCUIT EVALUATION; CIRCUIT TECHNIQUES; CONTENTION REDUCTION; DELAY CHARACTERISTICS; DOMINO LOGIC CIRCUITS; SPEED ENHANCEMENT; VARIABLE THRESHOLDS;

LOGIC CIRCUITS;

EID: 0742328321     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASIC.2002.1158077     Document Type: Conference Paper

References (5)

1. V. Kursun and E. G. Friedman, "Low Swing Dual Threshold Voltage Domino Logic," Proceedings of the ACM/SIGDA Great Lakes Symposium on VLSI, pp. 47-52, April 2002.
2. A. Alvandpour, P. Larsson-Edefors, and C. Svensson, "A Leakage Tolerant Multi-Phase Keeper for Wide Domino Circuits," Proceedings of the IEEE International Conference on Electronics, Circuits and Systems, pp. 209-212, September 1999.
3. A. Alvandpour, R. Krishnamurty, K Soumyanath, and S, Borkar, "A Low Leakage Dynamic Multi-Ported Register File in O.13μm CMOS," Proceedings of the IEEE International Symposium on Low Power Electronics and Design, pp. 68-71, August 2001.
4. M. W. Allam, M. H. Anis, and M. I. Elmasry, "High-Speed Dynamic Logic Styles for Scaled-Down CMOS and MTCMOS Technologies," Proceedings of the IEEE International Symposium on Low Power Electronics and Design, pp. 155-160, July 2000.
5. I. S Hwang and A, L. Fisher, "Ultrafast Compact 32-bit CMOS Adders in Multiple-Output Domino Logic," IEEE Journal of Solid-State Circuits, Vol. 24, No. 2, pp 358-369, April 1989