Self calibrating circuit design for variation tolerant VLSI systems

Proceedings - 11th IEEE International On-Line Testing Symposium, IOLTS 2005

Volumn 2005, Issue , 2005, Pages 100-105

  Kim, Chris H ^a   Hsu, Steven ^b   Krishnamurthy, Ram ^b   Borkar, Shekhar ^b   Roy, Kaushik ^b  

^a UNIVERSITY OF MINNESOTA   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC CIRCUIT PERFORMANCE; LEAKAGE SENSOR DESIGNS; PROCESS COMPENSATING DYNAMIC (PCD) CIRCUIT; TEST CHIP;

INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; NANOTECHNOLOGY; ROBUSTNESS (CONTROL SYSTEMS); SENSITIVITY ANALYSIS; SIGNAL TO NOISE RATIO;

VLSI CIRCUITS;

EID: 33745484581     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2005.63     Document Type: Conference Paper

References (9)

1. S. Borkar, "Low power design challenges for the decade", Asian Pacific Design Automation Conference, pp. 293-296, Jan. 2001.
2. S. Yang, S. Ahmed, B. Arcot, R. Arghavani, P. Bai, S. Chambers et al., "A high performance 180 nm generation logic technology", International Electron Devices Meeting, pp. 197-200, Dec. 1998.
3. C.H. Kim, K. Roy, S. Hsu, A. Alvandpour, R. Krishnamurthy, and S. Borkar, "A process variation compensating technique for sub-90nm dynamic circuits", Symposium on VLSI Circuits, pp. 205-206, June 2003.
4. A. Alvandpour, R. Krishnamurthy, K. Soumyanath, and S. Borkar, "A conditional keeper technique for sub-0.13μ wide dynamic gates", Symposium on VLSI Circuits, pp. 29-30, June 2001.
5. 2 SRAM cell", International Electron Devices Meeting, pp. 61-64, Dec. 2002.
6. C.H. Kim, K. Roy, S. Hsu, R. Krishnamurthy, and S. Borkar, "An on-die CMOS leakage current sensor for measuring process variation in sub-90nm generations", Symposium on VLSI Circuits, pp. 250-251, June 2004.
7. M.M. Griffin, J. Zerbe, G. Tsang, M. Ching, and C.L. Portmann, "A process-independent, 800-MB/s, DRAM byte-wide interface featuring command interleaving and concurrent memory operation", IEEE Journal of Solid-State Circuits, Vol. 33, Issue 11, pp. 1741-1751, Nov. 1998.
8. T. Kuroda, T. Fujita, S. Mita, T. Nagamatu, S. Yoshioka, F. Sano, et al., "A 0.9V 150MHz 10mW 4mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme", International Solid-State Circuits Conference, pp. 166-167, 437, Feb. 1996.
9. A. Dancy and A. Chandrakasan, "Ultra low power control circuits for PWM converters", IEEE Power Electronics Specialists Conference, Vol. 1, pp. 21-27, 1997