Wire optimization for multimedia SoC and SiP designs

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 55, Issue 8, 2008, Pages 2202-2215

  Lee, Jaesung ^a   Lee, Hyuk Jae ^a  

^a Seoul National University   (South Korea)

Author keywords

Multimedia system on chip (SoC); On chip bus; SoC Network Protocol (SNP); System in package (SiP); VLSI design; Wire efficiency

Indexed keywords

EFFICIENCY; INTERNET PROTOCOLS; MOTION PICTURE EXPERTS GROUP STANDARDS; MULTIMEDIA SYSTEMS; PROGRAMMABLE LOGIC CONTROLLERS; SILICON COMPOUNDS; SYSTEM-IN-PACKAGE; VLSI CIRCUITS; WIRE;

ADVANCED HIGH PERFORMANCE BUS; ADVANCED MICRO-CONTROLLER BUS ARCHITECTURE; ANALYSIS AND SIMULATION; INTEGRATION TECHNOLOGIES; ON-CHIP BUS; REGISTER TRANSFER LEVEL; STATIC PERFORMANCE ANALYSIS; VLSI DESIGN;

SYSTEM-ON-CHIP;

EID: 54749139322     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.920153     Document Type: Article

References (30)

1. W. Krenik, D. D. Buss, and P. Rickert, "Cellular handset integration-SIP versus SoC," IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1839-1846, Sep. 2005.
2. T. Brandtner, "Chip-package codesign flow for mixed-signal SiP designs," IEEE Design Test Comput., vol. 23, pp. 196-202, May-June 2006.
3. C. A. Zeferino, M. E. Kreutz, L. Carro, and A. A. Susin, "Models for communication trade-offs on system-on-chip," in Proc. Int. Workshop IP-Based SoC Design, Oct. 2002, pp. 394-394.
4. C. T. Hsieh and M. Pedram, "Architectural energy optimization by bus splitting," IEEE Trans. Comput.-Aided Des., vol. 21, no. 4, pp. 408-414, Apr. 2002.
5. T. Seceleanu, J. Plosila, and P. Liljeberg, "On-chip segmented bus: A self-timed approach," in Proc. IEEE 15th ASIC/SOC Conf., Sep. 2002, pp. 216-221.
6. K. K. Ryu, E. Shin, and V. J. Mooney, "A comparison of five different multiprocessor SoC bus architectures," in Proc. EUROMICRO Symp. Digit. Syst. Des., Sep. 2001, pp. 202-209.
7. "AMBA Specification," Rev. 2.0, Axis. Sunnyvale, CA, 1999.
8. "CoreConnect Bus Architecture," IBM. Yorktown Heights, NY, 1999.
9. "SuperHyway On-Chip Interconnect Solution," SuperH. San Jose, CA, 2003.
10. "CoreFrame Architecture," Palmchip. San Jose, CA, 2002.
11. "STBus Interconnect," STMicroelectronics. Geneva, Switzerland, 2004.
12. "Wishbone Bus," OpenCores, 2003.
13. "AMBA AXI Protocol Specification," Axis. Sunnyvale, CA, 2003.
14. "Virtual Component Interface Standard," VSI Alliance, 2000.
15. "Open Core Protocol Specification," OCP International Partnership, 2001.
16. L. Benini and G. De Micheli, "Network on chips: A new SoC paradigm," IEEE Comput., pp. 70-78, Jan. 2002.
17. T. T. Ye, L. Benini, and G. D. Micheli, "Packetized on-chip inter-connect communication analysis for MPSoC," in Proc. IEEE Design Autom. Test Eur., Mar. 2003, pp. 344-349.
18. D. Wingard, "MicroNetwrok based integration for SoCs," in Proc. IEEE Design Autom. Test Eur., Jun. 2001, pp. 673-677.
19. P. Guerrier and A. Greiner, "A generic architecture for on-chip packet switched interconnections," in Proc. IEEE Design Autom. Test Eur. Mar. 2000, pp. 250-256.
20. M. B. Taylor, J. Kim, J. Miller, F. Ghodrat, B. Greenwald, P. Johnson, W. Lee, A. Ma, N. Shnidman, V. Strumpen, D. Wentzlaff, M. Frank, S. Amarasinghe, and A. Agarwal, "The raw processor - A scalable 32-bit fabric for embedded and general purpose computing," in Proc. Hotchips Conf. XIII, Aug. 2001.
21. W. H. Ho and T. M. Pinkston, "A methodology for designing efficient on-chip interconnects on well-behaved communication patterns," in Proc. 9th. Int. Symp. High-Performance Comput. Arch., Feb. 2003, pp. 377-388.
22. Y.-S. Cho, E.-J. Choi, and K.-R. Cho, "Modeling and analysis of the system bus latency on the SoC platform," in Proc. Int. Workshop System-Level Interconnect Prediction, Mar. 2006, pp. 67-74.
23. D. D. Gajski, N. Dutt, A. Wu, and S. Lin, High-Level Synthesis: Introduction to Chip and System Design. Boston, MA: Kluwer Academic, 1992.
24. G. D. Micheli and M. Sami, Hardware/Software Co-Design. Boston, MA: Kluwer Academic, 1997.
25. S. Even, Graph Algorithms. Baltimore, MD: Computer Science Press, 1979.
26. S.-M. Kim, "Hardware-software implementation of MPEG-4 video codec," ETRI J., vol. 25, no. 6, pp. 489-502, Dec. 2003.
27. E. Salminen, K. Kuusilinna, and T. D. Hamalainen, "Comparison of hardware IP components for system-on-chip," in Proc. Int. Symp. System-on-Chip, Nov. 2004, pp. 69-73.
28. S. Wimer, S. Michaely, K. Moiseev, and A. Kolodny, "Optimal bus sizing in migration of processor design," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 5, pp. 1089-1100, May 2006.
29. P. Caputa and C. Svensson, "Well-behaved global on-chip interconnect," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 2, pp. 318-323, Feb. 2005.
30. T. Kim, X. Li, and D. J. Allstot, "Compact model generation for on-chip transmission lines," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 3, pp. 459-470, Mar. 2004.