Modeling and analysis of the system bus latency on the SoC platform

International Workshop on System Level Interconnect Prediction, SLIP

Volumn 2006, Issue , 2006, Pages 67-74

  Cho, Young Sin ^a   Choi, Eun Ju ^a   Cho, Kyoung Rok ^a  

^a Chungbuk National University   (South Korea)

Author keywords

Latency; Multi layer bus; Platform; SoC; System bus

Indexed keywords

COMPUTER SIMULATION; DATA COMMUNICATION SYSTEMS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; THROUGHPUT; VELOCITY MEASUREMENT;

LATENCY; MULTILAYER BUS; PLATFORMS; SOC; SYSTEM BUS;

SYSTEMS ANALYSIS;

EID: 33750919748     PISSN: None     EISSN: 15445631     Source Type: Conference Proceeding    
DOI: 10.1145/1117278.1117293     Document Type: Conference Paper

References (14)

1. W.O. Cesario, D. Lyonnard G., G. Nicolescu, Y. Paviot, Sungjoo Yoo, A.A. Jerraya, L. Gauthier and M. Diaz-Nava, "Multiprocessor SoC platform: a component-based design approach", Design & Test of Computers, IEEE, vol. 19, no. 6, pp. 52-63, Dec. 2002.
2. K. Keutzer, A.R. Newton, J.M. Rabaey and A. Saniovanni-Vineentelli, "System-level design: orthgonalization of concerns and platform-based design", Computer-Aided Design of Integrated Circuits and Systems, IEEE, vol. 19, no. 20, pp. 1523-1543, Dec. 2002.
3. Li Li, Minglun Gao, Zuoren Cheng, Duoli Zhang and Shuzhuan He, "A new platform-based orthogonal SoC design methodology", ASIC, 2003 Proceedings, on 5th International Conference, vol. 1, no. 3, pp. 428-432, Oct. 2003.
4. Kyeong Keol Ryu, Eung Shin, V.J. Mooney, "A comparison of five different multiprocessor SoC bus architectures," in Proc. of Euromicro Symposium on Digital Systems, Design, pp. 202-209, Sept. 2001.
5. Wen-Tsuen Chen, Jang-Ping Sheu, "Performance analysis of multiple bus interconnection networks with hierarchical requesting model," IEEE Trans. on Computers, vol. 40, no. 7, pp. 834-842, Jul. 1991.
6. Qing Yang, Laxmi N.Bhuyan, "Analysis of packet-switched multiple-bus multiprocessor system," IEEE Trans. On Computers, vol. 45, no.5, pp. 580-588, May. 1996
7. John L.K.,Yu-cheng Liu, "Performance model for a prioritized multiple-bus multiprocessor system," IEEE Trans. On Computers, vol. 45, no.5, pp.580-588, May. 1996.
8. th Symposium on Integrated Circuits and Systems Design, pp.121-126, Sept.2002.
9. AMBA specification Rev2.0, ARM co., May 1999.
10. S.Okada, N. Takada, H. Miura and T. Asaeda, " System-on-a-chip for digital still camera with VGA-size clip shooting", Consumer Electronics, IEEE, vol. 46, no. 3, pp. 622-627, Aug. 2000.
11. MaxSim developer suite user's guide Ver 5.0, AXYS Design Automation Inc., Mar. 2004.
12. th Symposium on Integrated Circuits and Systems Design, pp.121-126, Sept. 2002.
13. Furber. S, "Future Trends in SoC Interconnect". 2005 IEEE International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). pp. 295-298, April 2005
14. Sang Hun Lee, Chan Ho Lee, Hyuk Jae Lee, "A New multi-channel on-chip-bus architecture for system-on-chips" Proc. of IEEE International SOC Conference, pp.305-308, Sept. 2004.