Chip-package codesign flow for mixed-signal SiP designs

IEEE Design and Test of Computers

Volumn 23, Issue 3, 2006, Pages 196-202

  Brandtner, Thomas ^a  

^a INFINEON TECHNOLOGIES AUSTRIA AG   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS PACKAGING; FLIP CHIP DEVICES; MICROELECTRONICS; PRODUCT DESIGN;

CHIP-PACKAGE CODESIGN FLOW; SYSTEM-IN-PACKAGE;

INTEGRATED CIRCUIT LAYOUT;

EID: 33744505901     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2006.65     Document Type: Article

References (10)

1. R.R. Tummala and V.K. Madisetti, "System on Chip or System on Package?" IEEE Design & Test of Computers, vol. 16, no. 2, Mar.-Apr. 1999, pp. 48-56.
2. A. Fontanelli et al., "System-on-Chip (SoC) Requires IC & Package Co-design and Co-verification," Proc. IEEE Custom Integrated Circuits Conf. (CICC 02), IEEE Press, 2002, pp. 319-322.
3. A.K. Varma, A. Glaser, and P.D. Franzon, "CAD Flows for Chip-Package Coverification," IEEE Trans. Advanced Packaging, vol. 28, no. 1, Feb. 2005, pp. 96-101.
4. R.R. Tummala, ed., Fundamentals of Microsystems Packaging, McGraw-Hill, 2001.
5. LEF/DEF Exchange Format, Version 5.6, Silicon Integration Initiative (Si2); http://openeda.si2.org/projects/lefdef/.
6. Virtuoso Custom Design Platform, Cadence; http://www.cadence.com/ products/custom_ic/.
7. OpenAccess, Version 2.2, Silicon Integration Initiative (Si2); http://www.si2.org/openaccess/.
8. Allegro Package Designer, Cadence; http://www.cadence.com/products/ si_pk_bd/apd_apsi/.
9. AIF Data Exchange Format, Artwork Conversion Software; http://www.artwork.com/package/aif/.
10. PakSi-E Extraction Tool, Optimal Corp.; http://www.optimalcorp.com.