Well-behaved global on-chip interconnect

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 52, Issue 2, 2005, Pages 318-323

  Caputa, Peter ^a   Svensson, Christer ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

Global interconnect; Interconnect; Interconnect delay; On chip bus; Upper level metal

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC IMPEDANCE; ELECTRIC LINES; ELECTRIC WIRE; INDUCTANCE; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS;

GLOBAL INTERCONNECT; INTERCONNECT DELAY; ON-CHIP BUS; ON-CHIP INTERCONNECT; UPPER LAYER METAL;

DIGITAL INTEGRATED CIRCUITS;

EID: 14644394900     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2004.840483     Document Type: Article

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