-
1
-
-
84944390453
-
Beating in-order stalls with "Flea-Flicker" two-pass pipelining
-
BARNES, R. D., NYSTROM, E. M., SIAS, J. W., PATEL, S. J., NAVARRO, N., AND HWU, W. W. 2003. Beating in-order stalls with "Flea-Flicker" two-pass pipelining. In Proceedings of the 36th International Symposium on Microarchitecture.
-
(2003)
Proceedings of the 36th International Symposium on Microarchitecture
-
-
BARNES, R.D.1
NYSTROM, E.M.2
SIAS, J.W.3
PATEL, S.J.4
NAVARRO, N.5
HWU, W.W.6
-
3
-
-
0032662989
-
Simultaneous subordinate microthreading
-
CHAPPEL, R. S., STARK, J., KIM, S. P., .REINHARDT, S. K., AND PATT, Y. N. 1999. Simultaneous subordinate microthreading. In Proceedings of the 26th International Symposium on Computer Architecture. 186-195.
-
(1999)
Proceedings of the 26th International Symposium on Computer Architecture
, pp. 186-195
-
-
CHAPPEL, R.S.1
STARK, J.2
KIM, S.P.3
REINHARDT, S.K.4
PATT, Y.N.5
-
4
-
-
0034839033
-
Speculative precomputation: Long-range prefetching of delinquent loads
-
COLLINS, J. D., WANG, H., TULLSEN, D. M., HUGHES, C., LEE, Y.-F., LAVERY, D., AND SHEN, J. P. 2001. Speculative precomputation: Long-range prefetching of delinquent loads. In Proceedings of the 28th International Symposium on Computer Architecture.
-
(2001)
Proceedings of the 28th International Symposium on Computer Architecture
-
-
COLLINS, J.D.1
WANG, H.2
TULLSEN, D.M.3
HUGHES, C.4
LEE, Y.-F.5
LAVERY, D.6
SHEN, J.P.7
-
6
-
-
31844456792
-
Automatically partitioning packet processing applications for pipelined architectures
-
DAI, J., HUANG, B., LI, L., AND HARRISON, L. 2005. Automatically partitioning packet processing applications for pipelined architectures. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation. 237-248.
-
(2005)
Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation
, pp. 237-248
-
-
DAI, J.1
HUANG, B.2
LI, L.3
HARRISON, L.4
-
7
-
-
0036959649
-
A stream compiler for communication-exposed architectures
-
GORDON, M. I., THIES, W., KARCZMAREK, M., LIN, J., MELI, A. S., LAMB, A. A., LEGER, C., WONG, J., HOFFMANN, H., MAZE, D., AND AMARASINGHE, S. 2002. A stream compiler for communication-exposed architectures. In Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems. 291-303.
-
(2002)
Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems
, pp. 291-303
-
-
GORDON, M.I.1
THIES, W.2
KARCZMAREK, M.3
LIN, J.4
MELI, A.S.5
LAMB, A.A.6
LEGER, C.7
WONG, J.8
HOFFMANN, H.9
MAZE, D.10
AMARASINGHE, S.11
-
8
-
-
0033880036
-
The Stanford Hydra CMP
-
HAMMOND, L., HUBBERT, B. A., SIU, M., PRABHU, M. K., CHEN, M., AND OLUKOTUN, K. 2000. The Stanford Hydra CMP. IEEE Micro 20, 2, 71-84.
-
(2000)
IEEE Micro
, vol.20
, Issue.2
, pp. 71-84
-
-
HAMMOND, L.1
HUBBERT, B.A.2
SIU, M.3
PRABHU, M.K.4
CHEN, M.5
OLUKOTUN, K.6
-
12
-
-
85008034312
-
Efficiently evaluating speedup using sampled processor simulation
-
LUO, Y. AND JOHN, L.K. 2004. Efficiently evaluating speedup using sampled processor simulation. Comput. Architect. Lett.
-
(2004)
Comput. Architect. Lett
-
-
LUO, Y.1
JOHN, L.K.2
-
13
-
-
33749375700
-
Automatic thread extraction with decoupled software pipelining
-
OTTONI, G., RANGAN, R., STOLER, A., AND AUGUST, D. I. 2005. Automatic thread extraction with decoupled software pipelining. In Proceedings of the 38th IEEE/ACM International Symposium on Microarchitecture.
-
(2005)
Proceedings of the 38th IEEE/ACM International Symposium on Microarchitecture
-
-
OTTONI, G.1
RANGAN, R.2
STOLER, A.3
AUGUST, D.I.4
-
14
-
-
0007091743
-
Multiprocessors: Discussion of some theoretical and practical problems
-
Tech. Rep. UIUCDCS-R-79-990 Nov, Department of Computer Science, University of Illinois, Urbana, IL
-
PADUA, D. A. 1979. Multiprocessors: Discussion of some theoretical and practical problems. Tech. Rep. UIUCDCS-R-79-990 (Nov.). Department of Computer Science, University of Illinois, Urbana, IL.
-
(1979)
-
-
PADUA, D.A.1
-
15
-
-
33748307265
-
Rapid development of a flexible validated processor model
-
PENRY, D. A., VACHHARAJANI, M., AND AUGUST, D. I. 2005. Rapid development of a flexible validated processor model. In Proceedings of the 2005 Workshop on Modeling, Benchmarking, and Simulation.
-
(2005)
Proceedings of the 2005 Workshop on Modeling, Benchmarking, and Simulation
-
-
PENRY, D.A.1
VACHHARAJANI, M.2
AUGUST, D.I.3
-
16
-
-
10444243253
-
Decoupled software pipelining with the synchronization array
-
RANGAN, R., VACHHARAJANI, N., VACHHARAJANI, M., AND AUGUST, D. I. 2004. Decoupled software pipelining with the synchronization array. In Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques. 177-188.
-
(2004)
Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques
, pp. 177-188
-
-
RANGAN, R.1
VACHHARAJANI, N.2
VACHHARAJANI, M.3
AUGUST, D.I.4
-
17
-
-
40349096761
-
Support for high-frequency streaming in CMPs
-
RANGAN, R., VACHHARAJANI, N., STOLER, A., OTTONI, G., AUGUST, D. I., AND CAI, G. Z. N. 2006. Support for high-frequency streaming in CMPs. In Proceedings of the 39th International Symposium on Microarchitecture. 259-269.
-
(2006)
Proceedings of the 39th International Symposium on Microarchitecture
, pp. 259-269
-
-
RANGAN, R.1
VACHHARAJANI, N.2
STOLER, A.3
OTTONI, G.4
AUGUST, D.I.5
CAI, G.Z.N.6
-
18
-
-
33749484001
-
-
RO, W. W., CRAGO, S. P., DESPAIN, A. M., AND GAUDIOT, J.-L. 2006. Design and evaluation of a hierarchical decoupled architecture. J. Supercomput. 38, 3 (Dec.), 237-259.
-
RO, W. W., CRAGO, S. P., DESPAIN, A. M., AND GAUDIOT, J.-L. 2006. Design and evaluation of a hierarchical decoupled architecture. J. Supercomput. 38, 3 (Dec.), 237-259.
-
-
-
-
22
-
-
33745198176
-
The stampede approach to thread-level speculation
-
STEFFAN, J. G., COLOHAN, C., ZHAI, A., AND MOWRY, T. C. 2005. The stampede approach to thread-level speculation. ACM Trans. Comput. Syst. 23, 3, 253-300.
-
(2005)
ACM Trans. Comput. Syst
, vol.23
, Issue.3
, pp. 253-300
-
-
STEFFAN, J.G.1
COLOHAN, C.2
ZHAI, A.3
MOWRY, T.C.4
-
24
-
-
33746072606
-
A framework for unrestricted whole-program optimization
-
TRIANTAFYLLIS, S., BRIDGES, M. J., RAMAN, E., OTTONI, G., AND AUGUST, D. I. 2006. A framework for unrestricted whole-program optimization. In ACM SIGPLAN 2006 Conference on Programming Language Design and Implementation. 61-71.
-
(2006)
ACM SIGPLAN 2006 Conference on Programming Language Design and Implementation
, pp. 61-71
-
-
TRIANTAFYLLIS, S.1
BRIDGES, M.J.2
RAMAN, E.3
OTTONI, G.4
AUGUST, D.I.5
-
25
-
-
0033344478
-
The superthreaded processor architecture
-
TSAI, J.-Y., HUANG, J., AMLO, C., LILJA, D. J., AND YEW, P.-C. 1999. The superthreaded processor architecture. IEEE Trans. Comput. 48, 9, 881-902.
-
(1999)
IEEE Trans. Comput
, vol.48
, Issue.9
, pp. 881-902
-
-
TSAI, J.-Y.1
HUANG, J.2
AMLO, C.3
LILJA, D.J.4
YEW, P.-C.5
-
26
-
-
84983179859
-
Microarchitectural exploration with Liberty
-
VACHHARAJANI, M., VACHHARAJANI, N., PENRY, D. A., BLOME, J. A., AND AUGUST, D. I. 2002. Microarchitectural exploration with Liberty. In Proceedings of the 35th International Symposium on Microarchitecture. 271-282.
-
(2002)
Proceedings of the 35th International Symposium on Microarchitecture
, pp. 271-282
-
-
VACHHARAJANI, M.1
VACHHARAJANI, N.2
PENRY, D.A.3
BLOME, J.A.4
AUGUST, D.I.5
-
29
-
-
84949755841
-
Memory latency-tolerance approaches for Itanium processors: Out-of-order execution vs speculative pre-computation
-
WANG, P. H., WANG, H., COLLINS, J. D., GROCHOWSKI, E., KLING, R. M., AND SHEN, J. P. 2002. Memory latency-tolerance approaches for Itanium processors: Out-of-order execution vs speculative pre-computation. In Proceedings of the 8th International Symposium on High-Performance Computer Architecture. 187-196.
-
(2002)
Proceedings of the 8th International Symposium on High-Performance Computer Architecture
, pp. 187-196
-
-
WANG, P.H.1
WANG, H.2
COLLINS, J.D.3
GROCHOWSKI, E.4
KLING, R.M.5
SHEN, J.P.6
-
30
-
-
51149112181
-
-
WENISCH, T. F., WUNDERLICH, R. E., FALSAFI, B., AND HOE, J. C. 2004. TurboSMARTS: Accurate microarchitecture simulation sampling in minutes. Tech. Rep. 2004-003 (Nov.). Computer Architecture Lab at Carnegie Mellon.
-
WENISCH, T. F., WUNDERLICH, R. E., FALSAFI, B., AND HOE, J. C. 2004. TurboSMARTS: Accurate microarchitecture simulation sampling in minutes. Tech. Rep. 2004-003 (Nov.). Computer Architecture Lab at Carnegie Mellon.
-
-
-
-
31
-
-
0038346244
-
SMARTS: Accelerating microarchitecture simulation via rigorous statistical sampling
-
WUNDERLICH, R. E., WENISCH, T. F., FALSAFI, B., AND HOE, J. C. 2003. SMARTS: Accelerating microarchitecture simulation via rigorous statistical sampling. In Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA). 84-97.
-
(2003)
Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA)
, pp. 84-97
-
-
WUNDERLICH, R.E.1
WENISCH, T.F.2
FALSAFI, B.3
HOE, J.C.4
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